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Why are OR gates used with shorted inverted inputs, effectively acting as NOT gates in this circuit? (Page 9 of this datasheet.)

What's the difference with directly putting a NOT gate, other than having a bigger capacitive load due to the transistors gates? Is it to have a bigger delay?

Why does the inverter between 14 and 15 has its inverting bubble drawn at the input and not at the output?

Also I guess the output inverters are put in parallel in order to increase the driving capability, i.e. to lower the output resistance.

(p.9 of https://cdn-reichelt.de/documents/datenblatt/B400/ULTRASCHALL%20SENSOR.pdf)

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    \$\begingroup\$ Take it up with Murata or just live with it. After all, is it that big of a deal if someone tries to be a little ornate in the diagrams; it's not as if they don't make sense. \$\endgroup\$ – Andy aka Mar 11 at 10:30
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    \$\begingroup\$ they just drawn them oddly, 4011 is 4 NAND gates, and 4049 is 6 inverters. YCLIU \$\endgroup\$ – Jasen Mar 11 at 10:47
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    \$\begingroup\$ An OR gate would not act as inverter when shorted. You need a NOR gate or a NAND gate for that. \$\endgroup\$ – PMF Mar 11 at 10:49
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    \$\begingroup\$ Probably because the gates don't come individually, they come with a certain number on a single chip, and if they did it the other way, they'd need more chips. \$\endgroup\$ – user253751 Mar 11 at 11:07
  • \$\begingroup\$ There are no OR gates on that circuit. Which is OK : you can't use an OR as an inverter anyway. \$\endgroup\$ – user_1818839 Mar 11 at 13:00
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It's a "bubble-matching" exercise where bubbles are matched to bubbles, and non-bubbles are matched to non-bubbles, which requires substituting some gates for De Morgan equivalents.

Bubble matches

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This is a (admittedly confusing) style that uses the DeMorgan equivalents.

For example the gate drawn as:

Inverted Input OR

is logically identical to:

NAND Gate

When you connect the two inputs as is done in this circuit, you get an INVERTER.

The "bubble input" gate is also identical to the more common INVERTER symbol.

As far as why they doubled-up the inverters driving the output transducer, I'm sure the reason is that they wanted more drive current to the transducer than a single gate could provide.

It's not at all clear why they drew this schematic in such a confusing manner. In my experience the DeMorgan equivalent gates are rarely used and then only to convey something about the logic. Here, it doesn't make any sense to me.

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  • \$\begingroup\$ Not confusing. Standard symbots are biased towards positive-logic. DeMorgan's symbols are negative-logic. A positive-input NAND is equivalent to a negative-input OR. Places emphasis on desired state of activation. So that a troubleshooter could isolate desired state. In this case, it's meaningless, but in it's day, it facilitated efficient transfer of knowledge from designer to troubleshooters. \$\endgroup\$ – StainlessSteelRat Mar 11 at 16:13
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When the Japanese do something weird, I initially assume there is a hidden reason before I consider it as a mistake.

This was just a handy way to make relatively high impedance (est. 200? Ohm= 200/2 + 200/2) full-bridge voltage doubler that cannot be done with 5V 74HC family logic.

Opinion

This is just a logical indication of usage for the same thing. To them, the dots might indicate something of greater significance, such as high input impedance or low output impedance even though these OR and NAND are the same logic and in the same IC. The same with the inverters. They both invert, but what's more important the high input impedance or the low output impedance or don't care (both needed).

First some CMOS background for some millenials.

  • When the 4xxx series CMOS logic 1st came out in the early '70's , it was very flexible for Vss from 3 to 18V (i.e. a 6:1 ratio) even though they might work from 2 to 20V off-spec with some loss in performance.
  • The symmetrical output impedance was a great feature over TTL and you had the choice of UB unbuffered gates and B, buffered gates. We knew how to measure this by checking Vol/Iol specs from max to typ
    • this is because of the exponential change in Ron above Vt often defined in FETs as Vgs(th)@ 300uA which translates to about 5V/2 / 300uA or Ron ~ 3kOhm (min) with a threshold of about 1.5V used in 4xxx series CMOS vs. 2 to 4V in power FETs.
  • then 74HCxxx CMOS came along and lowered the output impedance to 50 Ohms (+/- 50%, now towards +/-25%) but due to shoot-thru spikes, the Vss range had to be limited Vss= 2 to 6V ( or a 3:1 ratio) This lower impedance is why the ratio was reduced to 3:1 but smaller lithography and reduced input capacitance also means greater max frequency.

The weird stuff

  • You will notice from De Morgan's theorem, that the inverting input OR is equivalent to a NAND. ( Changing NAND to/from OR demands you invert both the output and inputs.)
  • Also the inverter on the input was common for TTL control signals yet on an "inverter" is logically identical to show on input or output. By "convention" we use the output, yet here the logic is being used as an analog driver.

Unusual

also I notice that the 4049B is now obsolete by TI and others.

I recall the CD4xxx family had a minimum analog voltage gain of 10 at 5V but higher at 10V. So you are certainly welcome to use more than 2 parallel CD4049 buffers in parallel. This will reduce Ron or Zout but not increase the voltage gain or rise time. As you can see from the datasheets the prop delay in the same family depends on the number of cascaded gates and not so much on the cascode multiple inputs of the NAND gate structure (not shown).

enter image description here

Also, notice the Piezo must be relatively high impedance compared to the 0.1uF series Cap at 40kHz ( i.e. much lower capacitance)) for this to be efficient.

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  • \$\begingroup\$ Uhhh ... No. "The Japanese" are following rules laid down by the US military in the 1950's. Hobby magazines used and explained this symbology in the 60's. Today they are a part of ANSI, IEC, and IEEE standards. \$\endgroup\$ – AnalogKid Mar 12 at 1:55
  • \$\begingroup\$ Really? To mix symbols on the same chip? @AnalogKid I know the symbols are valid, but I’ve seen a lot Military specs and docs in my 1st Aerospace job, and never seen this before . Citation on mixed use in 1 chip? \$\endgroup\$ – Tony Stewart EE75 Mar 12 at 2:21
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It is nice to see a schematic that is drawn "correctly". That is in quotes because it is correct, but way out of favor. Almost no one pays attention to showing the logic state polarity of a signal. In parallel with that, almost no one teaches DeMorgan transformation with the emphasis it deserves. This is part of the difference between a schematic diagram and a wiring diagram. When communicating a design concept, how a gate functions within the circuit is much more important than the traditional name for its part number. But that is a separate rant.

The idea is independent of any logic chip series (74xx, 4xxx, etc), technology (TTL, CMOS, etc.), or compexity (simple gates, multi-core CPUs, etc.). It has to do with which one of the two logic states (high / low, 0 / 1) are "active" - which state is the one that is important, the one that controls decisions, etc. A text description gets pretty fuzzy because there are so many different things these gates are used to do.

Using your schematic as an example, look at the 555 output signal on pin 3. It drives a standard inverter. With the bubble on the input, the schematic is saying that it is the low input state that is the "action state". This is called a "negative-true" inverter. When its input is low, its output is high and this is what causes something to happen; in this case, allowing the output of the two-gate oscillator to be passed through to the transducer. The NAND gate input also has no bubble, indicating that it is the high input that causes a desired action.

Looking at gates 4-5-6 and 8-9-10 (sure do miss reference designators), while these are usually described as NAND gates, the full name is a positive-true NAND gate. But in this circuit, the function as a negative-true device, and the negative-true transformation of a NAND gate is an OR gate. Showing a negative-true input follows one of the rules of this type of symbology - to preserve the correct logical polarity, a bubble always drives a bubble. If it doesn't, then you put a slash across the signal line next to the gate input where the standard depiction changes.

Technically, this type of schematic symbology still is required in military projects, although, again, almost no one does it this way anymore. When properly done, it makes a schematic page with maybe a hundred or more logic gates splattered around much easier to read (decipher?) without assistance from the original designer.

There is more to the logic symbol language than just bubbles. Texas Instruments played a huge roll in both the development of integrated circuit logic devices and the symbols used to describe them. Their datasheets still use them. The functional diagram of an 8-bit latch is just a box with pins and names, but the logic diagram has specific non-text designations for open-collector outputs, edge-triggered versus level-triggered clock inputs, etc.

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As for your other questions ...

  1. OR gates - as explained by others, this is an alternate depiction of a NAND gate that better shows its function in the circuit. Yes, they effectively are NOT gates.

  2. Difference - In this circuit there is not difference. The circuit requires an inverter in those two locations, and NAND sections work perfectly well for that. Depending on the internal circuitry, there might not be any difference in propagation delay. If there is some, it is not enough to affect the circuit's operation in any way.

  3. Input pins shorted together - this has nothing to do with input capacitance. An unused logic input has to be dealt with correctly. If left floating (unconnected to anything), it can act as a noise antenna, causing erratic gate operation. Also, floating CMOS inputs can cause the gate to go into a half-on/half-off stuck in the middle of the transition region place that greatly increases the gates power dissipation. Since most logic gates have all of the inputs next to each other, a convenient way to terminate an unused gate is to tie it to its neighbor. It is equally acceptable to tie an unused gate either high or low, depending on which state does not affect the rest of the circuit.

  4. Paralleled sections - Yes, this is to increase the output current capability. The channel resistance of a CMOS gate's transistors act as an output resistor making direct-parallel connections safer than with other logic families. TTL parts do not have nearly as large an effective output resistance, and direct parallel connections like this are expressly forbidden in high-reliability applications. Many companies in this field do not draw such a distinctions, and forbid this type of connection for all logic types.

The concern is that even with identical parts, or two gates in the same package, the two gates do not transition at ((exactly)) the same input voltage. No matter how rapidly the input voltage changes, there is a nanosecond or three when one output stage is high and the other is low, causing cross-conduction between the power rail and GND (sometimes called a "shoot-through" current). No matter how brief, over time this degrades the output transistors and shortens the device's life. When it comes to designing for long-term reliability, this is a very real thing.

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