I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining bits.
This arrangement causes a setup violation (negative slack) in the data-path. The first rising edge is the latch edge (because the first bit is already available). The second rising edge launches the second bit. The launch clock lags the latch clock by 130 degrees. The period of the clock is 10ns. The path report indicates that Timing Analyzer thinks that the latch edge is 3.5ns after the launch edge. However, in reality, the latch edge is 6.5ns after the launch edge. So I just need to tell Timing Analyzer that it is mistaking the latch edge for the launch edge (and vice versa). This is the problem.
Is there a good timing exception for this scenario? I don't want to use "set_false_path" because I need the path analyzed.