I have been given a prompt to design a 7 segment display using NOR gates. My understanding of the prompt (8.R) is:
Design an excess-2 code converter to drive a 7 segment display. Design the display using two, three, and four input NOR gates and inverters. Any solution that uses 16 gates and inverters or fewer (not counting the four inverters for the inputs) is acceptable.
Using K-Maps, I have derived seven POS equations that I converted to NOR gates through double inversion.
| Segment | POS Equations | NOR Gate Implementation |
|---|---|---|
| 1 | (A + B + D')(B' + C' + D) | [(A + B + D')' + (B' + C' + D)']' |
| 2 | (A' + C + D)(B' + C' + D') | [(A' + C + D)' + (B' + C' + D')']' |
| 3 | (A + C + D) | [(A + C + D)']' |
| 4 | (A + B + D')(A' + C + D')(B' + C' + D) | [(A + B + D')' + (A' + C + D')' + (B' + C' + D)']' |
| 5 | (D')(A' + C' + D) | [D + (A' + C' + D)']' |
| 6 | (A + C + D)(C + D')(A + B + D') | [(A + C + D)' + (C + D')' + (A + B + D')']' |
| 7 | (A + B)(A' + C + D') | [(A + B)' + (A' + C + D')']' |
To reduce the number of gates, some are reused. These gates are (A + B + D')', (B + C + D')', and (B' + C' + D)'.
Afterward, my logic diagram looks like this:
The Problem
Counting up the logic gates on my diagram (excluding the inverters from the inputs A through D), I count 17 gates. This does not satisfy the requirements of the prompt. Therefore, I am thinking I messed up somewhere along the way, either in:
- Deriving POS gates from my K-Maps
- Reusing shared gates
I'm lost as to what I could improve to reduce my gate count by one. Any ideas?
