0
\$\begingroup\$
module test1(input logic A,B,C,D);
 output reg Y; 
 always@(A,B,C,D) begin
  case({A,B,C,D})
    4'b0011: Y<=1;
    4'b0111: Y<=1;
    4'b1100: Y<=1;
    4'b1101: Y<=1;
    4'b1111: Y<=1;
    4'b1110: Y<=1;
    4'b1010: Y<=1;
    default: Y<=0;
  endcase
 end
endmodule

The above Verilog code is showing the following error:

------- Error Output --------------
test_bench.v:12: error: port ``y'' is not a port of dut.
1 error(s) during elaboration.

What is the issue?

\$\endgroup\$
1
  • 1
    \$\begingroup\$ well, y is not a port of dut tells you what's wrong. Your problem is in test_bench.v in line 12. We don't know your line numbering, so you're the one who needs to help yourself. \$\endgroup\$ Mar 12, 2021 at 7:32

1 Answer 1

5
\$\begingroup\$

According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with the following syntax:

list_of_port_declarations ::=
      ( port_declaration { , port_declaration } )
     | ( )
port_declaration ::=
      {attribute_instance} inout_declaration
     | {attribute_instance} input_declaration
     | {attribute_instance} output_declaration

That means that for your design the ports declaration should be the following:

module test1
(
    input logic A,B,C,D, 
    output reg Y 
);
\$\endgroup\$
0

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