I think I just don't fully understand shift registers made from D-flip-flops as in http://en.wikipedia.org/wiki/Shift_register

Why does it shift only one bit per pulse? As I look at it it just seems to me that it should shift everything and rewrite with SI at the single pulse.

I think my problem of understanding this origins at D-flip-flop, somewhere I've read that it stores the value only on rising-edge, but the way it's implemented doesn't seem like it to me. It seems like it can store value at any time the clock is at 1 (even change multiple times during single clock pulse).


Notice the arrow-head symbol on the clock input of each of the flip-flops. This indicates (rising) edge triggering.

Shift Register

This means that each time the clock signal transitions from low to high, the signal at D gets copied over to Q.

In the ideal case the clock edge is instantaneous, so whichever level is applied at D at that instant, is all that matters.

Even in practical situations where the clock rise time is finite, triggering is at the transition of the clock past a threshold value. Thus, the read-in from D remains instantaneous.

  • \$\begingroup\$ Thanks for answer, As a friend explained to me, it looks I've mistaken D-latch and D-flip-flop (which is made of two latches with alternate clock). Guess I will accept this so the question is closed. But thnx again. Didn't know about the arrows in the diagram, will be useful :) \$\endgroup\$ – Honza Brabec Jan 17 '13 at 7:33
  • \$\begingroup\$ Triggering is not instantaneous. Triggering takes a finite amount of time, and if the input changes during that window, it will be impossible for the manufacturer to guarantee both of the following: (1) if after the normal propagation time the output is high, it will remain high until the next clock pulse; (2) if after the normal propagation time the output is low, it will remain low until the next clock pulse. A manufacturer may opt to ensure that one or the other condition is always met, but if e.g. the manufacturer opts to ensure the first... \$\endgroup\$ – supercat Jan 17 '13 at 15:59
  • \$\begingroup\$ ...then there will be a risk that a clock pulse might not cause the output to go high immediately, but spontaneously switch high at some future time. Suppose, for example, that when the output is low a clock arrives near a falling edge of data, and time zero represents the latest time data would have to fall, relative to the clock, to ensure that the data output would never go high, and T represents the time when the output would go high "cleanly", then if the input switches at time t where 0 < t < T, the output might not switch until time a-b * log(t/T), for some constants a and b. \$\endgroup\$ – supercat Jan 17 '13 at 16:14
  • \$\begingroup\$ Constant a would represent the propagation delay, and b would represent a metastability factor. Note that as t approaches T, the log term will go to zero, but as t approaches zero, the log term will get arbitrarily big. If there's any random variation on t, the probability of the log term exceeding a particular value will fall off very quickly; in practice, a chip with a 10ns propagation time is probably more likely to get smashed by a meteor than have its output switch a second late, but an output switching 50ns late should not be unexpected if timing constraints are violated. \$\endgroup\$ – supercat Jan 17 '13 at 16:20

When using D latches for a shift register, it's absolutely imperative that the guaranteed minimum propagation time for each flop exceeds the maximum required hold time for the next. If that condition were not met, it would indeed be possible for one clock pulse to end up trashing the contents of all the bits. For some reason, manufacturers often don't specify the timings for their parts in such a way as to guarantee that those timing constraints will be met (minimum guaranteed propagation time is often zero, while hold times are sometimes positive) but in practice, for flops within a chip, and usually for all the flops within a batch of chips, any factors which would cause the hold time to be at the high end of its range will cause the propagation time to also be at the high end of its range, and vice versa.

Incidentally, when implementing a shift register within a CPLD or FPGA, the normal approach is to use D latches; when implementing them in silicon, though, other approaches may be more efficient. In many cases, a device will use two transparent latches per bit, with alternate latches activated by different non-overlapping clocks. One could further improve upon the spacial efficiency of this by having groups of N bits each represented using N+1 latches strobed by N+1 clocks [the common method has N=1, but going to N=2 would represent a 33% reduction in the number of latches] but I'm not aware of that being done in practice.

Also, FYI, if one can guarantee that data will be continuously shifted at some minimum rate, it's possible to reduce the transistor count to 3 per latch [or two transistors and a passive pull-up]. The video memory for the original Apple I computer used 1Kbit shift registers which were in 8-pin DIP packages and were, from what I've read, by far the cheapest form of memory available. I don't think such techniques are used much anymore, since they rely upon a certain relationship between transistor leakage and gate-source, gate-drain, and gate-substrate capacitances, but I still find them interesting.


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