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I have a big design implemented in Verilog. The design has FIFO as shown in the image below. Due to some reason I have to add a new "Consumer" block shown.

The issue is, this block needs all the rows from the source block (FIFO in this case, which I cannot modify) simultaneously in single clock. What should I do? what intermediate block I can implement that will satisfy the requirement of the Consumer block. Right now the read pointer is reading data sequentially.

enter image description here

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  • \$\begingroup\$ If you can't modify the source, and it doesn't output all its rows somewhere, then there's no possible way of getting the data out of it in one clock cycle? \$\endgroup\$
    – pjc50
    Commented Jan 17, 2013 at 10:14
  • \$\begingroup\$ @pjc50 But I am allowed to put an additional block between source and consumer. The source and consumer may work asynchronously. \$\endgroup\$
    – gpuguy
    Commented Jan 17, 2013 at 10:18
  • \$\begingroup\$ You could empty the fifo into a 23x6 array, one row at a time, and then copy it across to the consumer - is that satisfactory? If extra data arrives in the FIFO in the meantime it won't be included. \$\endgroup\$
    – pjc50
    Commented Jan 17, 2013 at 10:32
  • \$\begingroup\$ Does 'expecting all 23 rows in single clock' mean that you must have exactly 23 valid data units or can there be less? Is the data b/w FIFO and Consumer pushed by the FIFO, or pulled/requested by the Consumer? If no other module is connected to the FIFO you could replace it by a shift register or put the shift register as a intermediate module b/w FIFO and consumer(as pjc50 proposed). \$\endgroup\$
    – andrsmllr
    Commented Jan 17, 2013 at 10:42

2 Answers 2

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Two options:

  1. Either You need 23 times faster clock and read the data with that clock.
  2. Read FIFO using the same sequential reading method, but burst all the data to output after the data is read. This will result in 23 times larger data burst because of 23 times larger data bus.
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Reshaping the bus from 6 bytes wide to (23*6) 138 bytes wide you will have a less frequently asserted 'valid' signal going into the consumer. Serial-in to parallel-out is usually best implemented with shift-registers and a counter to assert valid out every 23 valid input cycles. Your shift register consist of 48 independent single-bit shift registers, each 23 elements deep.

You can load the shift register either from the input to the FIFO, or the output from the FIFO depending on the clock domains and buffering characteristics required. E.g does Consumer need several/veriable cycles in which the wide input is held? In which you need the FIFO to buffer the transient rate mismatch.

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