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I've got a pretty simple circuit here where main regulator is powered either from battery or from USB source. When USB power is conected Q2 is closed and battery is charged by MCP73831 at the same time as system is powered from USB bus via D3 diode (PMEG4010 in my case).

The problem that I'm facing is that even if I'm using a very low leakage Schottky diode (PMEG4010 should have less than 7uA reverse leakage current at 10V, while I only have max 4.2V LiPo voltage) I still have around 0.8V at Q2 gate. This is taking into account that my R3 is already 10kOhm, not 100k as per the image below. Maybe I don't understand something? Why gate voltage of Q2 is not going closer to GND?

Previously I was using a B130LAW Schottky diode and Gate voltage was about 1.03V. So switching to PMEG4010 definitely helped, but still the result is quite strange to me.

My circuit is based on circuit from here and yes, I've read all the comments about pull-down resistor to fix the Schottky diode reverse leakage current, but if that current is around 10uA than 10kOhm should be more than enough to bring Q2 gate voltage down to almost 0V, but that's not happening.

https://blog.zakkemble.net/a-lithium-battery-charger-with-load-sharing/

Please have a look at my schematic. I'm talking about the situation when no VCC_USB is present and system is powered from VCC_BAT only, so Q2 should be open because R3 pulls VCC_USB net down opening Q2 MOSFET. Thanks for help!

P.S. You can ignore MCP130T and TPS63060 circuits as they're not relevant to my question.

enter image description here

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PMEG leakage is only 1uA @ 25’C but rises quickly to 100uA at 85’C so thermal leakage is significant.

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  • \$\begingroup\$ Yep but the diode is definitely not at 85C, there's actually no load connected to TPS63060 when I'm measuring the gate of Q2, so everything can be considered to be at 25C. \$\endgroup\$
    – Lt_Flash
    Mar 13, 2021 at 16:47
  • \$\begingroup\$ What is Vusb with 10M DMM? When disconnected? \$\endgroup\$ Mar 13, 2021 at 16:48
  • \$\begingroup\$ It goes up if I increase R3 resistance, originally I had 100kOhm and VCC_USB was about 1.8V. \$\endgroup\$
    – Lt_Flash
    Mar 13, 2021 at 16:50
  • \$\begingroup\$ So then add current probe to simulation and find where the leakage is. The simulator could be making the wrong assumptions, in part, on temp or worst case also record Vgs vs Id. I suspect you are seeing Idss or I at Vt \$\endgroup\$ Mar 13, 2021 at 16:52
  • \$\begingroup\$ I'm measuring the actual circuit, not a simulation, that's why I'm confused. I was expecting the gate of Q2 to go down almost to 0V but that's not happening so my question is - maybe I'm overlooking something? The only thing that comes to my mind is to remove D3 completely and see what happens to the gate of Q2 and if it goes to 0V than it means that PMEG4010 is still leaking much more than it should be as per datasheet, am I right? \$\endgroup\$
    – Lt_Flash
    Mar 13, 2021 at 16:55

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