# Why do we need NMOS transistors for NAND gate?

I have a hard time understanding how gates are built from CMOS transistors. For example, I don't understand why do we need the NMOS transistors if the PMOS transistors will already produce the desired outputs?

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current

if one of the inputs X or Y will be 1 , then one of the switches will be open and there will be current flow, so the output will be 1.

it is only when both X and Y are 1 the current wont flow.

so, why do I need the NMOS transistors at the bottom then???

• what would you use instead? Commented Mar 13, 2021 at 20:19
• The NMOS transistors are unnecessary if you want to implement some sort of current-mode logic where absence of current is a logical zero. If you want to implement voltage-level logic, like typical CMOS or TTL, you'll need an active element to drive the zero voltage. A floating output is indeterminate, and the voltage will depend purely on the loads and will often not be what you want, so that wouldn't work when the inputs are voltage sensitive. Commented Mar 14, 2021 at 2:04
• @Kubahasn'tforgottenMonica The earliest MOS logic ICs used only PMOS transistors with pull-down resistors in place of the NMOS transistors used in CMOS. This approach was supplanted by NMOS and then CMOS designs as fabrication technology improved. en.wikipedia.org/wiki/PMOS_logic Commented Mar 14, 2021 at 19:18
• In the past they did do so, but they ate a lot of power. One of the main CMOS advantage is that it drains only during switching (almost) Commented Mar 15, 2021 at 10:38
• Whatever source this is, it's using wildly nonstandard symbols. I've never seen those symbols for MOSFETs before. Commented Mar 15, 2021 at 14:58

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current.

The output will not be '0', it will be floating.

• That will leave any connected devices with a floating input and very susceptible to noise.
• The connected devices also have input capacitance and these need to be discharged to drive the inputs to logic 0.
• For high-speed logic the inputs must be switched quickly. The way to do this is to pull high and pull low directly.

Figure 1. Note that if we leave X and Y floating that it may be possible for the inputs to float to a stage where both the NMOS and PMOS transistors are partially on resulting in "shoot-through". In this state enough current passes through the devices and they heat up and can burn out.

• and what if I need just copy the signal though a transistor? do I have to include both (nmos and pmos) or just any of those can be used? Commented Mar 13, 2021 at 22:58
• If you want a non-inverting AND gate then you follow the NAND with an inverting stage. (NANDs are quicker than ANDs because there is one less propagation delay.) You'll need both the high side PMOS switches and the low side NMOS switches in the inverter as well. Have a look at the "fan-out" capability of the chips to see how many inputs one output can drive reliably. (It differs for each logic family.) Commented Mar 13, 2021 at 23:10
• @Nulik regarding your question about AND gate, take a look at this question : electronics.stackexchange.com/q/533533/238188 Commented Mar 15, 2021 at 5:21

You make the common, and mistaken, assumption that a node that is not actively driven (has zero current flowing) must be at a low voltage. That is not true.

The output of the gate must be pulled down or it can not operate reliably. Without a pull down of some kind the output voltage is indeterminate. You could use a resistor pulldown but that will waste a lot of power and/or be slower than an NMOS pulldown.

An NMOS transistor acts as a very low resistance between the output and the negative supply when its input is high. Here when X and Y are high, the two seried NMOS becoming just like wires will force the output to be low (FALSE).

In all 3 other cases the upper transistors, one or both, will force the output to be high (TRUE). If the NMOS transistors were missing, the output would just be floating like an antenna, hence capturing any parasitic signals and limiting the operational bandwidth.

Moreover that bandwidth could further be reduced because of the natural capacity of the circuit boards, or even semiconductor wafers used to build the system. Forcing the output to "low" would discharge immediately this capacity charged during "high" period.

• Concise but accurate explanation... I like such figurative explanations as "the two seried NMOS becoming just like wires" and, in such situations, I usually say the element behaves like a "piece of wire"... Only, it is interesting to see what happens in the middle, when two "wires" in series short the power supply... Commented Mar 15, 2021 at 8:11

When we call an undriven node "floating" we do it for one very good reason. Electrical nodes (wires) capacitively and inductively couple charge from all over the place. The basic principle is why motors and generators do what they do: charge is coupled between the rotor and stator windings. In motors and generators, this is desirable. In the world of microelectronics, we call this undesirable effect crosstalk.

Crosstalk is coupled from everywhere: other nearby nodes including signal nodes (wires used to transmit data) and clock nodes (evil little badgers when it comes to crosstalk), the power plane, the ground plane, and the substrate. Capacitive and inductive modeling for very high speed signal paths is detailed (bordering on enormous) literally for this one reason alone. Not-cutting-edge designs often only focus on the capacitive element because the wire lengths aren't long enough for the inductive element to matter as much and, as a result, simulation time is greatly reduced. Really-not-cutting-edge designs often lump capacitances together to further speed up the simulations.

My point is, without doing something to guarantee a signal node will be driven high AND low, the node's voltage will bounce all over the place. In the designs I worked on, it wasn't uncommon for the voltage to jiggle around 75% of Vcc simply because no insulator (including your substrate) is perfect. This is a frankly massive problem as the 75% transition point is usually within the metastable region of CMOS operation (the region where the circuit doesn't quite know whether it wants to be high or low, meaning it's moderately resistive and sensitive to crosstalk).

For completeness, consider that one pair or the other of your MOS transistors can be replaced with a single resistor (depending on which pair you pick, connected to Vcc or Gnd). This will work great so long as the ratio between the MOS on-resistance and the resistor is enough to allow the signal voltage to clear the gate-off voltage, but it will be power-hungry and slow. (In some of my old designs a very small NMOS transistor would be gate-to-drain connected to make it a resistive diode. We'd use this in reset circuits where the occasional pulse to reset something was so rare that the higher power loss and slower speed weren't an issue compared to the space savings of a full CMOS setup.)

My own background (from 30 years ago) was (is...) in BiCMOS design. Conceptually, a simple inverter was a 3-inverter device. The first CMOS inverter was very small. It drove a larger CMOS inverter, which then drove a Bipolar transistor array that had very, very small parallel CMOS devices. The result was a device that could drive an enormous amount of energy. (Usually data backplanes.) The technology was spectacularly good for 1V solutions on satellites.

But if you think about it, that means you have the traditional diode voltage drop. That's why we used the parallel CMOS devices, to guarantee full transition rather than a partial transition.

To summarize, when designing in a digital world, you want (a) full control over every data node and (b) as much control over capacitive and inductive coupling as possible. (A) is more important than (b) because you can't completely control (b).

• There is also a need for such in-depth answers from professionals in the field... I am too far from this reality but I am interested in the philosophy of things... the concepts. Here are some my thoughts... IMO a transformer is the best example of a useful inductive coupling... and data cables consisting of many wires - of an undesired coupling. The great idea behind the complementing NMOS transistor can be called dynamic pull-down "resistor". I have not understood the role of the NMOS transistor that is "gate-to-drain connected to make it a resistive diode" since IMO, it would be ever on. Commented Mar 15, 2021 at 8:46
• @Circuitfantasist The G-to-D connected NMOS would, indeed, always be on. Its value is that, in the design technologies I used at the time, it was physically smaller on the chip than an actual resistor of the same resistance. This was because the resistor was a surface object (the current flowed through something resistive above the substrate) while the NMOS was an embedded object (the current flowed through doped substrate, which is very high resistance to begin with). Should you focus on microelectronics, you'll discover many solutions like this where engineers make do with what they have.
– JBH
Commented Mar 15, 2021 at 14:51
• @Circuitfantasist The philosophy behind using the G-to-D NMOS is that we didn't care particularly what happened with the resistance. It simply had to be low enough to recharge (or discharge, in the case of a PMOS) the node in a timely fashion. Compare this to the need for an actual resistor in the circuit that must track with temperature and current density very precisely. In such a case the above-substrate resistor must be used. In microelectronics, design has more to do with the physics of the substrate than it does the schematic of the circuit.
– JBH
Commented Mar 15, 2021 at 14:54
• @Circuitfantasist We had all kinds of specialized hybrid devices that took advantage of the "quirks" of the substrate to minimize power consumption, maximize speed, and minimize layout space (the physical space on chip). Looking backward on my career, I learned as much in my first three years as an engineer as I did in my last three years of college.
– JBH
Commented Mar 15, 2021 at 14:55
• Hmmm ... microelectronics seems to be more physics than circuitry ... a lot of details, a few clear and simple ideas, analogies ... That's why I love basic circuitry, I'm interested in new combinations of old elements... Commented Mar 15, 2021 at 15:53

We can also use Pseudo-NMOS Logic, where we can use a single NMOS transistor in the pull-down network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.

• NMOS or PMOS in the pull-up network? And what is the idea of this topology? Commented Mar 15, 2021 at 8:57
• @Circuitfantasist thanks for pointing out the error. I've fixed it. Commented Mar 15, 2021 at 12:23

Your question is conceptual; so it can be answered by the help of well-known simple electrical concepts as voltage divider, potentiometer, rheostat...

Logic gates, like most digital and analog circuits, are devices with voltage inputs and outputs, ie, they are voltage-controlled voltage sources. Their output stages are implemented as voltage-controlled voltage dividers consisting of two elements in series. One of them (pull up) is connected to Vdd and the other (pull down) is grounded.

The main property of these "pulling" elements is resistance. But while in the simple resistor voltage divider their resistance is linear, in the output stages of electronic circuits it is nonlinear (dynamic); this causes them to switch quickly.

The output voltage of this voltage divider configuration is controlled by changing the resistance of one, the other or both elements (in opposite directions). For this purpose, they are implemented by transistors (MOSFET, BJT, etc.).

The output stage could be implemented by only one controlled element (transistor) connected to one of the supply rails only if a load with relatively low resistance is connected to the other rail. This configuration is called "open drain (collector)". Actually, the transistor and load constitute a voltage divider as above... but this is not the case here...

So, according to simple electrical concepts, in the case of a low-impedance load, we cannot change the output voltage with only one resistor (PMOSFET in your circuit) connected in series to the supply rail since there is no current flowing through and voltage drop across the resistor. We need another resistor (NMOSFET) connected to ground to provide a current and voltage drop across the upper PMOSFET.

The load can serve as such a resistor if it has relatively low resistance. If not, we have to connect another resistor to ground, in order to close the circuit.