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We would like to model a switching power supply for an LDMOS RF power amp so we can design the bias tee powering the drain to reflect as much RF as possible to keep RF out of the power supply. The signal will be around 144MHz.

We wish to keep the power supply model simple (if possible) and represent common 12V switching power supplies like those found in computers. In the picture below "PORT 6" is where the power supply will be attached in another circuit.

  • What output impedance should we assume that such a power supply might represent?
  • Are there any other considerations when modeling the DC power for the amp's drain-source?

(This video explains the project in more detail if you need more info or a picture of the whole circuit.)

FET Amp drain-source bias Tee

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    \$\begingroup\$ Model about 10nH/ cm per wire. so an RC filter may work. \$\endgroup\$
    – Tony Stewart EE75
    Mar 14, 2021 at 4:15
  • \$\begingroup\$ Rs//Cs might be harder to estimate, but if 1% step load regulation 12V @ 12A then 10 mOhm > 100 kHz and Caps TBD with same ESR \$\endgroup\$
    – Tony Stewart EE75
    Mar 14, 2021 at 4:42
  • \$\begingroup\$ Can you expand on your Rs//Cs comment? I'm not sure I understood. Do you mean that >100kHz the cap ESR should be ~20mOhm? \$\endgroup\$
    – KJ7LNW
    Mar 14, 2021 at 19:03
  • \$\begingroup\$ (^typo, I meant should cap ESR be 10mOhm?) \$\endgroup\$
    – KJ7LNW
    Mar 14, 2021 at 19:15

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