Multiple driver error for SystemVerilog initial value

Question

In my code I have an always_comb block coded as follows:

always_comb
begin
    if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
end

some_value and some_different_value. z is defined and given an initial value ( for simulation purposes ) as follows:

logic z = 42 ;

When I compile - I get an error: "Multiple drivers to always_comb output variable z detected". Is it a bug in the tool?

Answer 1

Get rid of the end before the else. The compiler is confused about where the first if ends.

Also,

• always_comb doesn't allow outside processes to write left-hand side variables (vs. always @ *, which does)
• regardless, more than one driver the same wire type is not allowed. The always_comb boils down to an assignment for z, so trying to assign it again outside results in the multi-driver error.

More about all that here: https://www.verilogpro.com/systemverilog-always_comb-always_ff/

And here: https://stackoverflow.com/questions/23101717/difference-among-always-ff-always-comb-always-latch-and-always

Finally, if your intention is for z to have some default value, careful coding style would include it in the body of the if-else statement as the final else. This is clearer for someone else reading your code (or yourself, later.)

Answer 2

You can write a statement inside the combinational block like this:

always_comb
begin
   z = 42; 
   if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
end

This statement before the if statement executes if none of the statements in the if statement are true. It is an alternative method of writing this:

always_comb
begin
    if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
    else
        z = 42;
end

If you write statements in both the else block and before the if condition statement, then the value assigned in the else block will be reflected and the other value will be ignored.

Note: Ensure all possible conditions are covered in the if statement for combinational logic!

If you really need a latch use always_latch, not always_comb!

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Regarding the concern of avoiding Xs in simulation, the best option is to declare the datatype as bit instead of logic. Doing so will initialise it to 0 since bit is 2-state.

Note: While 2-state simulation is faster, it is not recommended since it can cover up failure to initialise the hardware at start-up.