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In my code I have an always_comb block coded as follows:

always_comb
begin
    if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
end

some_value and some_different_value. z is defined and given an initial value ( for simulation purposes ) as follows:

logic z = 42 ;

When I compile - I get an error: "Multiple drivers to always_comb output variable z detected". Is it a bug in the tool?

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    \$\begingroup\$ Do you want to make an unclocked latch? AFAIK that's generally a bad practice - all registers (latches) should act on clock edges. \$\endgroup\$
    – user253751
    Mar 16, 2021 at 9:20

2 Answers 2

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Get rid of the end before the else. The compiler is confused about where the first if ends.

Also,

  • always_comb doesn't allow outside processes to write left-hand side variables (vs. always @ *, which does)
  • regardless, more than one driver the same wire type is not allowed. The always_comb boils down to an assignment for z, so trying to assign it again outside results in the multi-driver error.

More about all that here: https://www.verilogpro.com/systemverilog-always_comb-always_ff/

And here: https://stackoverflow.com/questions/23101717/difference-among-always-ff-always-comb-always-latch-and-always

Finally, if your intention is for z to have some default value, careful coding style would include it in the body of the if-else statement as the final else. This is clearer for someone else reading your code (or yourself, later.)

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  • \$\begingroup\$ The 'end' is a typo (fixed it). What if I want to avoid X's in simulation for the value of z ? In VHDL for example - I know it's perfectly legal to initialize combinatorial logic in such a way... \$\endgroup\$
    – shaiko
    Mar 15, 2021 at 16:34
  • \$\begingroup\$ For simulation, variables that get updated by multiple statements would be the ‘reg’ type. These would be part of a whole procedural block that contains the test vector set. ‘wire’ variables (either explicit or implicit) can have one and only one ‘assign’. \$\endgroup\$ Mar 15, 2021 at 16:39
  • \$\begingroup\$ Suppose (for some reason) you want to synthesize a latch (not a dff). And in simulation - you want this latch to have an initial value of 0. How would you code it ? \$\endgroup\$
    – shaiko
    Mar 16, 2021 at 1:01
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    \$\begingroup\$ Like any sequential element, if I care about its state at startup I code it with a reset. \$\endgroup\$ Mar 16, 2021 at 4:08
  • \$\begingroup\$ @shaiko also check this: electronics.stackexchange.com/q/550509/238188 \$\endgroup\$ Mar 16, 2021 at 15:23
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You can write a statement inside the combinational block like this:

always_comb
begin
   z = 42; 
   if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
end

This statement before the if statement executes if none of the statements in the if statement are true. It is an alternative method of writing this:

always_comb
begin
    if ( x == 0 )
        z = some_value ;
    else if ( y == 1 )
        z = some_different_value ; 
    else
        z = 42;
end

If you write statements in both the else block and before the if condition statement, then the value assigned in the else block will be reflected and the other value will be ignored.

Note: Ensure all possible conditions are covered in the if statement for combinational logic!

If you really need a latch use always_latch, not always_comb!


Regarding the concern of avoiding Xs in simulation, the best option is to declare the datatype as bit instead of logic. Doing so will initialise it to 0 since bit is 2-state.

Note: While 2-state simulation is faster, it is not recommended since it can cover up failure to initialise the hardware at start-up.

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    \$\begingroup\$ X is your friend! Don’t avoid or suppress it, fix the bugs where they occur. \$\endgroup\$
    – Michael
    Mar 16, 2021 at 6:27
  • \$\begingroup\$ @Michael I agree. \$\endgroup\$ Mar 16, 2021 at 8:38
  • \$\begingroup\$ So the bottom line is: "Verilog/Systemverilog simulation tools don't support default assignments for combinatorial logic ?" Correct ? \$\endgroup\$
    – shaiko
    Mar 16, 2021 at 14:12
  • \$\begingroup\$ @shaiko, you can use default statements in the else part of the if statement or as per the other code... It's not the tools but the language that stops you from assigning multiple drivers to a single logic datatype \$\endgroup\$ Mar 16, 2021 at 14:22

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