I am getting an error in my VHDL code. It says "[Synth 8-27] else clause after check for clock not supported". Why is this?

Below is the code:

library IEEE;
use work.Data_Sizes_Package.ALL;

entity Encoder_Counter is
  Port (Count_Input_A, Count_Input_B : in std_logic; 
        Reset_Counter : in std_logic;
        Counter_Value : out std_logic_vector(Data_width-1 downto 0)
end Encoder_Counter;

 architecture Behavioral of Encoder_Counter is

signal Counter_Value_Temp : std_logic_vector(Data_width-1 downto 0) := (others => '0');


Counter_Value <= Counter_Value_Temp;

    Process (Count_Input_A, Count_Input_B, Reset_Counter)
      if(rising_edge(Reset_Counter)) then
      Counter_Value_Temp <= (others => '0'); 
      elsif(rising_edge(Count_Input_A)) then
      Counter_Value_Temp <= Counter_Value_Temp + 1;
      elsif(rising_edge(Count_Input_B)) then
      Counter_Value_Temp <= Counter_Value_Temp + 1;      

      end if;

    end Process;

end Behavioral;
  • \$\begingroup\$ Where's the clock in your design !!????? You are designing a sequential circuit, you need a clock for that and all other inputs should be sampled on the rising edge of the clock. \$\endgroup\$ – Mitu Raj Mar 16 at 15:26
  • \$\begingroup\$ Get the fundamentals right: Add Clock, Reset in all sequential circuits. \$\endgroup\$ – Mitu Raj Mar 16 at 15:28
  • \$\begingroup\$ This question is a duplicate. \$\endgroup\$ – user8352 Mar 16 at 16:12
  • Your synthesis tool does not support multiple-clock registers.
  • Your code describes multiple clock registers.

That can't work.

  • \$\begingroup\$ Ok, this is essentially poorly written VHDL? Can this logic behaviour be achieved? Also this is intended to not be a clocked design. \$\endgroup\$ – David777 Mar 16 at 13:14
  • 1
    \$\begingroup\$ @David777 depends on the device you're targetting. But you would need either a time-reference (which, in a few comments, will become "yeah, you'll need a clock for that") or you need to use your input signals as clocks, because rising edge detection is a clock, even if it's a very irregular one. \$\endgroup\$ – DonFusili Mar 16 at 13:23
  • 1
    \$\begingroup\$ Since it's a counter it OUGHT to be a clocked design. You need to think more deeply about what hardware you are trying to create. \$\endgroup\$ – user_1818839 Mar 16 at 13:23
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    \$\begingroup\$ @David777 Yes, that is the correct way to solve your issue. Make sure to synchronize your inputs to your clock domain as well. \$\endgroup\$ – DonFusili Mar 16 at 14:18
  • 1
    \$\begingroup\$ @David777 In short: When taking a clock domain crossing between two non-synchronous clock domains, you can encounter metastability issues. These can be almost completely resolved by adding 2 FFs to the input signal that are clocked on the receiving clock before you read from the signal. There's more detailed explanations, but that's what Google/Educations are for. \$\endgroup\$ – DonFusili Mar 16 at 14:21

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