I am getting an error in my VHDL code. It says "[Synth 8-27] else clause after check for clock not supported". Why is this?
Below is the code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.Data_Sizes_Package.ALL; entity Encoder_Counter is Port (Count_Input_A, Count_Input_B : in std_logic; Reset_Counter : in std_logic; Counter_Value : out std_logic_vector(Data_width-1 downto 0) ); end Encoder_Counter; architecture Behavioral of Encoder_Counter is signal Counter_Value_Temp : std_logic_vector(Data_width-1 downto 0) := (others => '0'); begin Counter_Value <= Counter_Value_Temp; Process (Count_Input_A, Count_Input_B, Reset_Counter) begin if(rising_edge(Reset_Counter)) then Counter_Value_Temp <= (others => '0'); elsif(rising_edge(Count_Input_A)) then Counter_Value_Temp <= Counter_Value_Temp + 1; elsif(rising_edge(Count_Input_B)) then Counter_Value_Temp <= Counter_Value_Temp + 1; end if; end Process; end Behavioral;