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This is the pinout I have for the flash memory W25Q128FV which I'm trying to interact with

enter image description here enter image description here

I'm trying to control it with a raspberry pi 3 B+.

Here's how I wired everything:

CS - GND
D0 - SPIMISO
WP - nothing
GND - GND
VCC - 3.3v
HOLD - nothing
CLK - SPISCLK
DI - SPIMOSI

CS is in GND because datasheet says that in LOW, we can write/read from the chip.

I also enabled spi on raspberry and I'm using the library wiringPi with channel 0.

I'm writing like this:

wiringPiSPISetup(0, 2000000)
wiringPiSPIDataRW(0, data, 4)

but I get no changes in data. I suspect something is wrong but I don't know if it's on the chip, on the wiring or on the software. This is a brand new chip by the way.

What are the raspberry pins SPICS0 and SPICS1 for?

I'm trying to read the manufacturer id, here are the instructions:

enter image description here

here's what I did:

    data[0] = 0x90;
    data[3] = 0x00;
    data[4] = 0xEF;
    data[5] = 0x17;

I don't know what those MF7-MF0 and ID7-ID0 are but I substituted them by some numbers I found on the datasheet

datasheet link: http://www.xmcwh.com/Uploads/2020-09-03/5f50d26953af2.pdf

Here's my Rust code with everything ready to test and dockerized, just ./run.sh, compile the Wiringpi/wiringpi with ./build and cargo run in w25qxx_spi: https://github.com/lucaszanella/w25qxx_spi/blob/68a7f993a6572e177d9b4d60a7cfac02ccb016ff/w25qxx_spi/src/w25q.rs

If you help me you're helping open source, I'm interfacing with wiringpi in Rust and creating a library to read from W25Q spi flash memory.

Pins information:

enter image description here

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    \$\begingroup\$ So you updated the question and added bounty. Have you connected the memory chip CS to RPi yet, and have you changed your code to frame SPI transactions with the CS pin - At least the github repo has no updates on this. Can you also be more specifc where are you stuck and what kind of answer you want, as I already pointed out what the problem is - the CS needs to be used according to the protocol described in the datasheet to frame the commands, otherwise the SPI chip does not know which byte is the last byte of a transaction and which byte is the first byte of next transaction. \$\endgroup\$
    – Justme
    Commented Mar 19, 2021 at 10:09
  • \$\begingroup\$ @Justme it looks like CS should be triggered via GPIO, is that what you mean? I'm following github.com/nopnop2002/Raspberry-W25Q64/blob/master/main.c which is for the 64 version, and it does not do any triggering on GPIO. so that's why I'm confused about how to connect CS. I connected HOLD to 3.3v already. \$\endgroup\$
    – PPP
    Commented Mar 19, 2021 at 16:48
  • \$\begingroup\$ If so, then that library controls some GPIO pin as the chip select or it controls the hardware CS pin to do so. Also not all code on Internet works. I have no idea how various libraries on each platform works and that is a software problem. I suppose there are manuals for that library available or source code available to figure out how it works. \$\endgroup\$
    – Justme
    Commented Mar 19, 2021 at 17:35

2 Answers 2

Reset to default
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The normal connections for this device are:

  • CSn - use a CSn from the SPI interface. This is provided on your host. Also recommend a pull-up on this pin to deal with the host reset / startup case before the kernel has configured the pin. You must connect this pin to a valid CSn signal.
  • SCK - clock from the SPI interface
  • D0 / MOSI - 1-bit data input to flash
  • D1 / MISO - 1-bit data output from flash
  • D2 / WPn - Write Protect. Tie high with a pull-up, your host doesn't support it.
  • D3 / HOLDn - Hold. Tie high with a pull-up, your host doesn't support it.

The typical SPI sequence will use 1-bit (MOSI/MISO) to access registers and do initial setup and register access. On your platform you are limited to 1-bit data I/O as well.

This device also has 2-bit and 4-bit I/O, and uses specific dual- and quad-mode commands for read (doesn't seem to support that for writes though.) 4-bit doesn't apply to your platform, 2-bit might, but nevertheless you need to do something with the unused data I/O, as above.

Finally, the Winbond datasheet has detailed timing diagrams for all these kinds of accesses. In all of them, you will see that you absolutely must use CSn. This is how the device knows the beginning and end of an I/O transaction.

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  • \$\begingroup\$ Using the chip select 0 pin of raspberry pi worked, thanks \$\endgroup\$
    – PPP
    Commented Mar 25, 2021 at 16:26
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What is wrong is that CS is grounded and HOLD is not connected at all.

CS is used to frame the commands, so you need it, and HOLD must be held in correct level to keep the chip active.

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    \$\begingroup\$ the CS is usually driven from a gpio if your controller has no SPI transaction support. SPI memory need the CS to release to know when you are done with the data and need to send a new command or address (if in XIP), you can't simply keep it down forever \$\endgroup\$
    – Lorenzo Marcantonio
    Commented Mar 17, 2021 at 7:20
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    \$\begingroup\$ The datasheet has a whole chapter that detailedly describes the use of each pin, including the CS and HOLD pins. Do you have a specific question that the datasheet does not answer how to use the pins? \$\endgroup\$
    – Justme
    Commented Mar 17, 2021 at 8:08
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    \$\begingroup\$ @LucasZanella No it does not say that CS should be held permanently low. Please read chapter 7 to see diagrams how to use CS. Yes, HOLD should be at 3.3V. You can usually use search on PDF files to find stuff, try finding whether RESET high or low will keep the part in reset or lets it run. \$\endgroup\$
    – Justme
    Commented Mar 17, 2021 at 18:04
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    \$\begingroup\$ No. But you do need to use CS correctly. \$\endgroup\$
    – Justme
    Commented Mar 18, 2021 at 5:35
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    \$\begingroup\$ Try to read up more on SPI operations. The CS should be at high level when not interacting with the chip, but when it needs to send/receive data from the chip, you should manually pull CS low before interacting with the chip through SPI. The chip probably responds according to the CS line going low (falling edge), and then goes into a state where it waits for any SPI signals coming into the chip. After you are done communicating to the chip via SPI, you should pull the CS line high again. \$\endgroup\$
    – Cimory
    Commented Mar 24, 2021 at 20:46

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