I don't yet have a schematic but I am looking to reduce the power dissipation in linear voltage regulators in my circuit. The circuit is powered by a 24V switch mode power supply (110-240V AC to 24V DC) but I need three voltage rails of 12V, 5V and 3V.

What I intend to do is have three buck converters step down the 24V input to it's respective voltage output, before each linear regular to minimise the power dissipation e.g. 14V, 7V, 5V.

The reason for keeping the linear regulators is to minimise the switching noise as this circuit is making signal measurements. Would a design like this make sense attempting, and if so are there any general design rules that need to be considered?

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    \$\begingroup\$ Read my Rule of Thumb electronics.stackexchange.com/questions/553722/… and never start a design without specs for load regulation tolerance, no-load step overshoot, and ripple. For low current sometimes and RC filter is all you need. but you must define the load spectrum and error. \$\endgroup\$ – Tony Stewart EE75 Mar 17 at 19:33
  • \$\begingroup\$ I intend to buy some variable output buck converter modules to test the circuit first. I was just wondering if there are common rules for this sort of design as it must be a common implementation. \$\endgroup\$ – ChrisD91 Mar 17 at 19:36
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    \$\begingroup\$ Have you been to the Design Workbench at TI or AD? \$\endgroup\$ – Tony Stewart EE75 Mar 17 at 19:36
  • \$\begingroup\$ No, ive just Googled it and I'll check it out now. Thanks \$\endgroup\$ – ChrisD91 Mar 17 at 19:42
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    \$\begingroup\$ analog.com/en/design-center/ltpower-play.html \$\endgroup\$ – Tony Stewart EE75 Mar 17 at 19:51

I use a switcher/LDO combination in most of my designs and it works well. One problem is if you do use a switcher, a consideration that needs to be made is how much noise does the switcher emit in RF. Usually noise is not conducted by switchers into analog electroincs but it can emit electromagnetic noise from the switching and this can get picked up by sensors and cables.

I usually keep the switchers on a different board or partitioned from analog electronics. But YMMV as I am looking at nV and this might not be necessary in a 16-bit, 10uV's design.


Make sure you check the datasheet for the dropout voltage, for some LDO's it can be well over a volt. Better LDO's will spec better than 100mV (max voltage dropout is a column on digikey's (and probably mousers) search if looking at voltage regulators, so pick the one you want and the package that you want).

One thing that I do is if I need 5V I buy a 7805 (sic) 6.5V DC DC convert (they are in a pin compatable package) and then use an LDO to get the 1.5V, I'm wasting 1.5V but it's better than going from 15V to 5V.

  • \$\begingroup\$ My design is using a 12 bit ADC so that's approx. 800uv per bit @ 2.5V. Realistically, I've given myself a bit of room to average the signal out in code to remove anomalies. A separate board would be difficult for me due to room constrictions. Could I use something like a ferrite bead between the smps and the bucks and again between the buck to ldo? \$\endgroup\$ – ChrisD91 Mar 17 at 20:05
  • \$\begingroup\$ 800uV per a bit is a lot, it takes a lot of capacitive coupling to generate 800uV, for example if a switcher has 3mV RMS noise on it's output coupling a capacitor directly would give you 3/0.8 which would be 4 counts of bit noise. Air will be much much lower than a direct capacitor. In addition the signal might already be noisy. 12 bits shouldn't be hard to achieve with proper layout. Also make sure you account for any gains in the system a gain of 10 would yeild 80uV per bit on the input of the amplifier. \$\endgroup\$ – Voltage Spike Mar 17 at 20:09
  • \$\begingroup\$ I've got a gain of 100 in the system, to fill the signal across the ADC voltage range (the signal is a decay curve that is approximately 20mVpp). I have a 2nd order LPF with a cutoff of 100KHz with my smps switching at 1MHz and that seems to help a lot with impulse noise. I still have to mitigate noise in my passband however by using a digital averaging filter to smooth the curve out more. When I come to the layout of this circuit, I think ill have to ask more questions as I don't understand why you think 800uV is a lot per bit. My SMPS has voltage ripple of 120mVpp \$\endgroup\$ – ChrisD91 Mar 17 at 20:35
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    \$\begingroup\$ 800uV/bit is not that hard, 80nV/bit is. The higher V/bit you have the less you have to worry about noisy bits. 120mVpp is a lot for a power supply but not for a cheap one. \$\endgroup\$ – Voltage Spike Mar 17 at 20:46
  • \$\begingroup\$ Ahhh, I completely misunderstood what you meant! Thanks for clarifying \$\endgroup\$ – ChrisD91 Mar 17 at 21:01

As far as canned DC-DCs go, avoid cheap counterfeit junk, like everything that has a "LM2596" from the usual suspects like aliexpress or amazon. The only thing guaranteed is they will not meet their spec, and if there are electrolytic caps on them, you can bet they'll be garbage.

There are lots of inexpensive readymade products from trusted manufacturers...

If you don't make a pcb for your power supply, and you have 3 DC-DC modules with wires connected to the same input and output ground, then you have lots of ground loops with choppy current in them, which make nice loop antennas. Much better to put the 3 DC-DC modules on a PCB with a solid ground plane.

Input current is a square wave, so you need enough high-frequency ceramic caps there, and maybe a LC ferrite input filter to prevent the input current from becoming noise that is radiated by the input wires.

As far as output is concerned, that depends on the load, so you should look at each load in your design and consider:

  • Its max DC current

  • How much AC noise current it injects in its power supply depending on frequency.

  • How much ripple it can tolerate on its power supply depending on frequency.

For example:

  • microcontroller: wideband noise generator, doesn't care about noise on its supply.

  • opamp: unless feeding a low impedance load, doesn't make much noise, high PSRR ar low frequency, but low PSRR at high frequency

  • reference voltage for dac, adc, ratiometric sensor, etc: doesn't make much noise, but PSRR is essentially zero, noise on the reference voltage ends up in the output.

Then you partition your power rails into domains. For example, the MOSFET driver that draws 10ns 1Amp spikes (high HF noise) would not end up on the same +5V domain as the opamps that have low HF PSRR (thus high HF sensitivity).

Next, ponder which low frequency power supply impedance each domain requires. This will be low if it draws variable current and needs very stable voltage. But it can be a few ohms if it's an opamp that draws a few mA AC current and can tolerate the corresponding mV ripple due to its PSRR.

Next, all domains that can tolerate a bit of supply impedance are separated by LC filters with L being a ferrite bead. The bead should have good filtering at the offending frequencies, withstand the DC current without saturating, and not ring with the caps. The latter will usually require an electrolytic cap or a resistor in series. Get your ferrite spice models from murata.

So in the example above, the FET driver has its local decoupling cap which handles its HF current in a short local loop, then ferrite to main VCC rail, which has caps, then ferrite to opamp, which also has its local cap. So for a few cents worth of parts, you get a 5th order lowpass filter between the FET driver and the opamp, which means you probably don't need an extra LDO for the opamp.

If you use a bit higher voltage switcher followed by a LDO, you will get low ripple at low frequency, which opamps mostly won't care about. However at low dropout voltage, most LDO's PSRR suffers (check datasheets) and the input-to-output capacitance of the pass device also increases at low dropout, which means the HF ripple and spikes from the switcher go straight through the LDO. So, post-switcher LDO is a nice solution that works, but only if you actually need it, and if it is done right, with a LDO that has meaningful PSRR at the dropout voltage you will use and at the frequency where it matters.

Also the LDO does not replace ferrite beads.

Now the most sensitive node in your design is probably going to be the voltage reference for the DAC, ADC, or something like that. And that also draws very low current, which means you can use a linear regulator from a higher voltage rail or a low noise voltage reference IC without worrying about output current and dissipation. And you can also put a nice filter in the reference's input supply, since it draws low current this time you are allowed to put a highish value resistor in series with the ferrite to really pimp the mid-frequency PSRR.

Also you should not get married to your rail voltages. I suppose you use 12V for the opamps. They'll run just fine on 9V or 11V, or maybe even 5V. So if you have a special opamp that needs a special low noise supply, but doesn't use much current, like the first opamp in your signal chain that amplifies the tiny input signal... Then you can run it on a 5V or 9V linear regulator from your 12V rail. High dropout voltage, thus high PSRR ; low current thus low dissipation and RC filters are allowed too, not just LC.

  • \$\begingroup\$ I've avoided anything with the lm2596 as they all seem to have chunky electrolytic capacitors on the module and like you said, it looks like it wouldn't provide a good output. I have bought some modules with the and ceramic caps which I'm hoping has better performance. With the idea being, 220VAC > SMPS 24V DC > 17V DC MP1584EN > 15V lm7815 to reduce 24V to 15V with as little power dissipation across the lm7815 as possible \$\endgroup\$ – ChrisD91 Mar 18 at 21:11
  • \$\begingroup\$ Are you feeding the 12V 5V 3V3 switchers from the 7815? That sounds complicated \$\endgroup\$ – bobflux Mar 18 at 22:16

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