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Can I design a counter to increment on the clock rising edge?

For example, I am tying to create a counter that increments on the rising edge of the clock if an input is a logic level 1. If the input is a 0 on the clock rising edge, the counter is not incremented. When I write this logic, the code doesn't synthesise.

It seems like a counter enable signal I need after the clock edge detection but it won't synthesise.

EDIT

The error I am getting is:

[Synth 8-27] else clause after check for clock not supported [Synth 8-285] failed synthesizing module 'Encoder_Counter'

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Data_Sizes_Package.ALL;

entity Encoder_Counter is
  Port (Clock : in std_logic;
        Count_Input_A, Count_Input_B : in std_logic; 
        Reset_Counter : in std_logic;
        Counter_Value : out std_logic_vector(Data_width-1 downto 0)
       );
end Encoder_Counter;

 architecture Behavioral of Encoder_Counter is

signal Counter_Value_Temp : std_logic_vector(Data_width-1 downto 0) := (others => '0');

begin

Counter_Value <= Counter_Value_Temp;

    Process (Count_Input_A, Count_Input_B, Reset_Counter)
    
    begin
    
      if(rising_edge(Reset_Counter)) then   --rising or falling edge?????
      Counter_Value_Temp <= (others => '0'); 
            
      elsif(falling_edge(Clock)) then
                  
        if(Count_Input_A = '1' or Count_Input_B = '1') then
        Counter_Value_Temp <= Counter_Value_Temp + 1;      
        
        end if;
        
      end if;

    end Process;

end Behavioral;
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  • 1
    \$\begingroup\$ Please post your code and any error messages you are getting when you try to synthesize it. \$\endgroup\$ – jwh20 Mar 17 at 20:35
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I actually just found the error I was making that I learned on this forum from my last question.

The rising edge detection of the reset signal is synthesised like a clock, so when I try the falling edge detection for the real clock, it is unable to synthesise.

I changed the reset IF condition to checking for a logic level 1 instead of a edge and it now synthesises fine.

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  • \$\begingroup\$ You can put the corrected code in the answer. \$\endgroup\$ – Mitu Raj Mar 18 at 13:05
  • \$\begingroup\$ @MituRaj Will do when I get home. \$\endgroup\$ – David777 Mar 18 at 13:07

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