I know opinion based questions are not welcome but for a project I need to monitor 2MHz pulse train with 1ns ON times. Basically I need to monitor rising edges and if let's say the pulses are not 2MHz several times I want to shut down another system.

My problem is where to start for such a scenario. Would a uC suffice for such high speed application? or are there ad-hoc subsystems for such purposes. I dont want to re-invent the wheel.

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    \$\begingroup\$ Missing pulse designs are very much unique. Write spec on the tolerance and reaction times as well as the rise time, impedance and PW50 duration and allowed loading impedance to avoid reflections. This can be done with time interval counters and counters. 1ns or 500MHz pulses need careful detection \$\endgroup\$ – Tony Stewart EE75 Mar 18 at 12:41
  • \$\begingroup\$ 1 ns pulses are too short for the specs of most microcontrollers. The uC might be able to detect them, but I wouldn't rely on that. I would add external circuitry to stretch the 1nS pulse to (maybe) 250nS, which would be 50% duty cycle for a 2MHz train. \$\endgroup\$ – Math Keeps Me Busy Mar 18 at 12:44
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    \$\begingroup\$ It’s not hard to design, with/out uC but you must ! be precise in your spec tolerances \$\endgroup\$ – Tony Stewart EE75 Mar 18 at 12:44

So the system needs are

  1. Pulsewidth of 1ns
  2. Pulse frequency of 2MHz
  3. Be capable of detection one missing pulse 1/2e6

You have a period of 500ns and thus a duty of 0.2%.

You need to reliably detect that 1ns pulse, an asynchronous pulse to some clocked device so ideally you would have a device that can respond to an I/O change 2-3x faster than 1ns -> I/O clocking around 3GHz ... any slower and you are likely to miss the level change and thus generate false positives.

A uP is more than likely out of the question. An FPGA? maybe...

What could be done is a simple RC circuit to generate a signal that can be used as an interupt.

Buffer -> diode -> parallel RC -> Schmitt buffer -> I/O pin.

enter image description here

As long as the propagation delay of the buffer/schmitt is around 100ps you should be ok

Basically the rising edge of this pulse charges the RC network. When the signal goes low the RC network discharges. By setting the RC timeconstant such that it is 1.5x the period (with respect to the schmitt threshold), you would get a level change in the event of a single missing pulse

So propagation delays, rise times, what can detect or latch the resultant signal becomes key

  • \$\begingroup\$ It's an abstract answer that doesn't cover the larger problems. For example, how much source signal current will be needed to charge a capacitor in less than 1 ns. The capacitor must be relatively large for the Schmitt buffer leakage current and diode leakages to have a low effect on it. And so on, it's a bit of a wishful thinking answer, I'm afraid... \$\endgroup\$ – TonyM Mar 18 at 14:25
  • \$\begingroup\$ not that much of an abstract answer. I am using this exact circuit to detect loss of a 40MHz clock where this is the "stuck at 0 check". The concern however is the 1ns wide pulse and the impact this has on the down-selection of parts: leakage, propogation, risetime. For this however... the OP needs to provide some more work \$\endgroup\$ – JonRB Mar 18 at 14:51
  • \$\begingroup\$ But the difference between a 40 MHz square wave (12.5 ns mark) and the 1 ns pulse is where all the larger problems are. It doesn't mean this solution will definitely be applicable just with different values. Will have to downvote for those reasons, I'm afraid. \$\endgroup\$ – TonyM Mar 18 at 16:04

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