So the system needs are
- Pulsewidth of 1ns
- Pulse frequency of 2MHz
- Be capable of detection one missing pulse
You have a period of 500ns and thus a duty of 0.2%.
You need to reliably detect that 1ns pulse, an asynchronous pulse to some clocked device so ideally you would have a device that can respond to an I/O change 2-3x faster than 1ns -> I/O clocking around 3GHz ... any slower and you are likely to miss the level change and thus generate false positives.
A uP is more than likely out of the question. An FPGA? maybe...
What could be done is a simple RC circuit to generate a signal that can be used as an interupt.
Buffer -> diode -> parallel RC -> Schmitt buffer -> I/O pin.
As long as the propagation delay of the buffer/schmitt is around 100ps you should be ok
Basically the rising edge of this pulse charges the RC network. When the signal goes low the RC network discharges. By setting the RC timeconstant such that it is 1.5x the period (with respect to the schmitt threshold), you would get a level change in the event of a single missing pulse
So propagation delays, rise times, what can detect or latch the resultant signal becomes key