I'm just trying to visualize how the current flows in the following circuit. It is a follow-on question from here. The circuit is a small-signal model for a common-source MOSFET with source degeneration. In particular it is analysing the output resistance using voltage source Vx and measuring Ix. However, that is irrelevant to this question.

enter image description here

I have a few ideas, however I am pretty sure 1 and 2 are just outright wrong.

Explanation 1

enter image description here In this explanation, I was thinking that the VCCS is generating a current in that branch. That current must come from the node that is connected with Vx and ro. That gmvgs current will be sourced from the two branches depending on the impedance that the current 'sees'. Since Vx is an ideal voltage source, it must have 0 input impedance and hence the gmvgs current must all flow through that. This gives Ix = gmvgs.

Explanation 2

This explanation is very very flimsy.

enter image description here

In this explanation, I am also thinking about current division but from the point of view of the Ix current. Ix is flowing into the with the ro branch and VCCS branch. I thought that the current should divide according to its resistance. However the input resistance of a VCCS is not defined? This explanation seems completely wrong and my conclusion for this was that the current-source will pull that current no matter what, so current division isn't possible?

Explanation 3

This explanation seemed the most logical to me. enter image description here

In this explanation,

  • gmvgs flows from node X into node S, so it can be thought that a loop is formed with ro, since the VCCS will want gmvgs flowing into it and flowing out.
  • Now that the VCCS branch is happy, the Ix current must then flow through ro, through Rs and to GND.

If someone could just clarify these doubts in my mind that would great. I just would like to know why some of my explanations (or all) are incorrect and what is the correct way to go about thinking of this circuit, particularly when ideal elements are involved. Is current division still valid, since the series resistance of an ideal voltage source is 0?


In response to comment from Andy Aka: enter image description here

  • \$\begingroup\$ Due to the fact that the Vgs voltage is negative the gm*Vgs current will flow in the opposite direction (from S to D) that you have shown on your diagrams. \$\endgroup\$
    – G36
    Mar 18, 2021 at 17:10
  • \$\begingroup\$ @G36 not sure how you saw that Vgs is negative? \$\endgroup\$
    – Andy aka
    Mar 18, 2021 at 17:17
  • \$\begingroup\$ @Andyaka Gate terminal is directly connected to GND. \$\endgroup\$
    – G36
    Mar 18, 2021 at 17:18
  • \$\begingroup\$ @G36 oh OK, that may be an added confusion! \$\endgroup\$
    – Andy aka
    Mar 18, 2021 at 17:19
  • \$\begingroup\$ Ah yes. It was just convention in the book I read to always draw it like and then in the equations, you account for the minus. I should update it. \$\endgroup\$ Mar 18, 2021 at 17:21

2 Answers 2


The current \$I_X\$ (flowing from \$V_X\$) is made from two parts: -

  • \$g_m\cdot V_{GS}\$ and
  • the current flowing through \$R_0\$

The current flowing through \$R_0\$ = \$\dfrac{V_D - V_S}{R_0}\$

Also, you have shown the gate grounded in your circuit and that should not be the case.

  • \$\begingroup\$ Hmm. So none of the gmVgs current flows through Ro? (Explanation 3) \$\endgroup\$ Mar 18, 2021 at 17:23
  • \$\begingroup\$ If you had two parallel resistors across a power supply, does any current flowing in R1 flow through R2? \$\endgroup\$
    – Andy aka
    Mar 18, 2021 at 17:25
  • \$\begingroup\$ Absolutely not. But, the reason I say that current flows through Ro is because of what Razavi himself (design of analog cmos integrated circuits book author) mentioned in his book. See edit to original post - I added a picture from the book. The gate is grounded in this case because we are analysing the output resistance of a MOSFET circuit. VG had a DC + small-signal source on it. \$\endgroup\$ Mar 18, 2021 at 17:35
  • \$\begingroup\$ Well, that addition to your question has introduced another current source and a voltage Vbs but, fundamentally I don't see any discrepancy. \$\endgroup\$
    – Andy aka
    Mar 18, 2021 at 17:57

I think you are getting confused because you aren't thinking correctly about how the VCCS really works. A VCCS does not necessarily generate a current or limit a current, although it can be used to model that behavior in some circumstances.

In general, an ideal current source (whether dependent or independent) constrains the current passing through it. So don't say that the source generates or limits, just say that current through the source must be the specified value. When analyzing this circuit tell yourself that the current flowing through the VCCS must be \$g_m \times V_{GS}\$.

Once you have figured out the actual magnitude and direction of all currents and voltages you can figure out which elements are providing power to the circuit and which elements are absorbing power. Of course, you will soon develop an intuition for this and will be able to say from the beginning which elements are providing power, but until you develop that intuition stick to the defined behavior of an ideal current source: it constrains the current through it to a specified value.


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