Identifying decoupling capacitors in schematics and routing them properly to ICs

Question

I am a chemistry student trying to replicate a 4-layer PCB design from a pre-designed schematic. This is my first PCB project.

The design:

The stack:

• Signal/component top layer (jacks,pots,buttons)
• PWR internal plane
• GND internal plane
• Signal/component bottom layer (the layer with all the components).

General:

• An audio-signal processor (audio delay unit).
• Power consumption: +12V rail: 188mA max / -12V rail: 48mA max
• Digital power : 3.3 V
• Audio output : +10.5V to -10.5V maximum output
• Clock signal output : 0V to 8.2V

Main components:

• x1 MC - STM32F427ZGT6
• x1 Dram - AS4C16M16SA-7TCN
• x2 CODEC - CS4271-CZZ
• x7 Dual op-amps
• x6 JFET dual op-amp
• x1 Non-isolated DC/DC converters 3.3V 500MA OUT THRU - 78E-3.3-0.5

The full schematic can be found here.

Whilst I was routing my board I noticed that some of the capacitors were connected to both GND (from plane via) and PWR (3.3v, from plane via) and nothing else. I found this odd and then learned that these are presumably decoupling capacitors used to mitigate AC noise on DC power tracks. I then checked the schematic and found some seemingly random (to me) stand alone, sets of parallel connected capacitors in the schematics but thought nothing of it.

STM IC, presumed sets of parallel connected decoupling capacitors to the top right:

Sdram, with its presumed allocated set of decoupling capacitors:

Time output channel, with some presumed decoupling capacitors:

Clock output channels, with presumed decoupling capacitors for two channels but not all of them:

PWR section with presumed decoupling capacitors:

My questions:

How does one identify which set of decoupling capacitors should belong to a given IC/power chip? Why aren't these caps just connected straight to the IC in the schematic? Moreover, how does one route these capacitors to the pads of the IC?

My thoughts:

• Lets take the STM chip, it has 13 connections to that go straight (no resistor or capacitor connected in series) to 3.3V and 9 connections straight to GND. I was going to suggest that these should be placed in parallel between the 3.3V and the GND pads on the chip - but the set of parallel connected capacitors closest to the IC in the schematic consist of 2 sets of 6 parallel connected capacitors. So this seemingly doesn't add up.

A presumed example of this routing:

• Route/connect the capacitors together in parallel and then connect the 3.3 V/GND input/outputs in parallel to the respective pads. One set per two IC sides.

A presumed example of this routing (with 2 capacitors as an example):

Any thoughts would be greatly appreciated.

Answer 1

Why aren’t the caps connected straight to the chip in the schematic? That’s up to whoever draws the schematic. However, with larger chips with multiple pwr/gnd pins (eg: bga), it is common to divide the schematic symbol into multiple parts with one part being pwr/gnd pins. As for routing bypass caps - there’s been plenty written about this. Recently the same question was asked here and there were useful links. Basically you want to minimise the loop size between the chip and the cap. Placement of vias, track length/thickness all play a part. Choice of the actual capacitor can be critical - read the fine print on the likes of X7R and YUV caps. Just because it is a 10uF cap doesn’t mean you’ll actually get anywhere near that.

Generally bypass caps on analog is less critical - peak currents and frequencies are usually less. So putting 4 caps on a LM324 is probably not necessary.