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I am trying to understand how I can draw the layout of the following circuit where the 2 NMOSs have different body potential. Any suggestion will be highly appreciated.

Thanks!

enter image description here

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    \$\begingroup\$ Why not connect the bulk pin of M0 to DVSS? \$\endgroup\$
    – Andy aka
    Commented Mar 19, 2021 at 13:27
  • \$\begingroup\$ Doing this for research purposes actually. \$\endgroup\$
    – Shu
    Commented Mar 19, 2021 at 13:33

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  • In a bulk CMOS process there's only one P-substrate area so then you cannot make this circuit. All NMOS body contacts connect to the P-substrate and that is the only option.

  • If you have a triple well option available then it is possible to make a separate P-well (which which sits inside an N-well which sits inside the global P-substrate) then this is possible but realize that there will be (reverse biased) diodes between that "local Pwell" and the P-substrate.

  • If you have an SOI (Silicon On Insulator) process available (lucky you!) then you can make an isolated P-well for every NMOS.

So "how do I draw this" depends on the process you're using. It might not even be possible!

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  • \$\begingroup\$ I'm using TSMC 65nm process. We have NMOSs with N-well. Can you please add a bit more details about the feasibility of drawing triple-well using this process. Appreciate your detailed response earlier. \$\endgroup\$
    – Shu
    Commented Mar 25, 2021 at 19:08
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    \$\begingroup\$ We have NMOSs with N-well. All modern CMOS processes have N-well, without N-well you cannot make a PMOS. A triple-well is special and costs extra. You will have to consult the design manual to see if that is an option. I do not know how TSMC calls this as different foundries have different names for this. Have a look at this presentation to learen more: slideplayer.com/slide/8767883 Then look in the TSMC design manual if they offer something similar. \$\endgroup\$ Commented Mar 25, 2021 at 19:49
  • \$\begingroup\$ Thanks a lot for the explanation and the link. Appreciate your time and help. \$\endgroup\$
    – Shu
    Commented Mar 25, 2021 at 21:59
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What process are you using?

The majority of modern bulk CMOS processes (>180nm) have NMOS body connections directly to the p-substrate of the wafer, meaning there's only one, common substrate node for every N-type FET in the IC. PMOS devices are laid out in separate n-wells which allows distinct body connections.

If you are using a process that has both n-wells and p-wells you can put VIA contacts straight down into the well diffusion and connect it up how you like - but be aware there are usually DRC rules that specify minimum separations between wells due to parasitic capacitances that they introduce.

As a side note, you have not actually mentioned what you're trying to achieve with this circuit, it looks like an inverter with the top PMOS swapped out for an NMOS?

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  • \$\begingroup\$ I am working with TSMC 65 nm process. The reason for working with the circuit is we are trying to observe some characteristics behavior of MOSs where the body is connected to a different potential. \$\endgroup\$
    – Shu
    Commented Mar 19, 2021 at 18:22
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    \$\begingroup\$ I believe the TSMC 65nm kit is one of these standard processes that does not support pwells so you're not going to be able to observe body effects for individual NMOS devices. I suppose you could put contacts straight into the diffusion but I wouldn't recommend it for various reasons, one being the lack of defined area under influence (I'm not sure if it's even modelled). If you want to investigate the body effect you're going to have to use PMOS devices! \$\endgroup\$ Commented Mar 22, 2021 at 10:38
  • \$\begingroup\$ Thanks a lot for the suggestion @Alex Steven \$\endgroup\$
    – Shu
    Commented Mar 22, 2021 at 16:47

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