Forget about it. With 1 ms between each update, you need a very stable VCO that won't drift, which means a VCXO, which means $$$. You should only consider this option if you need ultra low phase noise, which you probably don't, since you mention 1µs drift is acceptable. No need to bother with the extra complication.
The master sends a message that means "Everyone gets ready to sample."
All the boards contain a simple logic gate like AND between the RS485 receiver output and the ADC "trigger sampling input". The micro sets a GPIO to 1, which drives the other input of the AND gate to 1. This means when the RS485 receiver outputs a logic "1", ADC will trigger sampling. Then the master reconfigures its UART output pin to GPIO, outputs a pulse that triggers all ADCs, then configures it back to UART. Once the sampling is done, all boards also reconfigure back to normal UART mode.
This does not need synchronization between the clocks, so you'll get one 40MHz cycle uncertainty between boards.
If the logic gate is too expensive, you can also use a pin change interrupt.
Each micro has its own free-running clock and ADC sampling.
When the RS482 synchro packet arrives, it is timestamped on the local clock.
Then, linear interpolation between the ADC sample taken before and the ADC sample taken after the synchro packet, to guess what the sample value would have been if it had been sampled at the arrival time of the synchro packet.
Pros: Free, no jitter to mess up the ADC.
Cons: Accuracy could be "meh", and if you are doing more elaborate things than just taking a sample value, you may not have stuff to interpolate.
Dumb and cheap solution
If the ADC is not sampling constantly, then just estimate when it should sample given the arrival times of the previous packets relative to the local clock, and trigger it at the right spot. You'll get an uncertainty of a few clock cycles, but that's less than the 1µs you say you need.
For example, say the master is running at 40 MHz and the slave runs at 39.9998 MHz. If you trigger the ADC every millisecond, that's every 40,000 cycles on the master. The slave would mark the arrival time of packets, do an average with some smoothing, and conclude it should sample every 39,999.8 cycles. You can do that with a PWm timer sending a pulse to trigger the ADC and a bit of code in the timer interrupt.
The Frac-N PLL
Local XO clock -> Fractional-N PLL. Either a separate chip, or in the micro if it has one.
The micro compares arrival times of synchro packets with output of fractional PLL, and adjusts the frequency to match. Make sure your Fractional PLL can be adjusted on the fly without losing lock, and has enough significant digits to be able to match the source frequency accurately enough without having to go bang-bang "too fast... too slow... too fast..."
Pros: will smooth out jitter over several synchro packets, pretty accurate, you can put whatever secret sauce you want in the loop filter to get the result you want
Cons: you need an extra chip and a PLL loop filter in software.
The Frac-N PLL with training wheels
Get a jitter attenuator like the CS2000. SureSiLabs has sexier chips, but you will pay extra for the very high frequency capabilities you won't actually use. CS2000 is simple: costs five bucks, give it a stable local clock, give it your 1kHz clock, set the registers via I2C to "multiply that by 40000" and done. It is also a Fractional-N PLL which means it has the stability of the local XO clock.
On the question of jitter
If you use the solutions that tweak sampling time, you get sampling jitter. That means the samples will be taken at slightly varying intervals. It is up to you to decide how much of it is okay in your application, that depends on the slew rate of your signal, ie how much it will change during the interval where it may be sampled. If it is a 1MHz sine wave, with 1µs timing uncertainty you get a random sample somewhere in the period, so it's completely useless. If it is DC, then jitter is irrelevant.
If you use the Frac-N PLL, you get a bit of jitter on the ADC clock, which will raise its noise floor. How much depends on the amount of jitter, the nature of the ADC, and the number of bits. The CS2000 specs 175 ps RMS max jitter, which is pretty low (caveat: jitter on the local reference clock has to be added to that of course). It's lower than a standard low-cost canned crystal oscillator, and much better than a crystal on a noisy micro. So it should be fine.