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Looking at the STCS1A datasheet I read:

Table 4. Thermal data

Symbol Parameter                           DFN8    Power SO-8 Unit
RthJC  Thermal resistance junction-case    10      12         °C/W
RthJA  Thermal resistance junction-ambient 37.6(1) 45(2)      °C/W

1.   This value is referred to four-layer PCB, JEDEC standard test board.
2.   With two sides, two planes PCB following EIA/JEDEC JESD51-7 standard.

About note 1: what is the standard here? The same as note 2 JESD51-7?

Here I read:

Summary of JEDEC Thermal, Multilayer Test-Board Specification JESD51-7

High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

Material: FR-4Layers: two signals (front and backside) and two planes (internal)
Finished thickness: 1.60 ±16mm
Metal thickness:
  - Front and backside: 2oz copper (0.070mm finished thickness)
  - Two internal planes: 1oz. copper (0.035mm finished thickness)
Dielectric layer thickness: 0.25mm to 0.50mm
Board size: 76.20mm x 114.30mm ±0.25mm for packages less than 27mm on a side

If I understand correctly the two values of the thermal resistance are valid only if the IC is placed alone on a such a huge board of 76x114 mm? I hope I'm wrong...

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  • \$\begingroup\$ That is correct as any other parts raise the near field ambient that affects case temp with convection cooling to the test board not enclosed. \$\endgroup\$ – Tony Stewart EE75 Mar 19 at 18:00
  • \$\begingroup\$ @TonyStewartSunnyskyguyEE75, got it. But because it's very unlikely that such a small package is put on a huge empty board, how should I take in account the actual space available? I mean, it seems a marketing ploy given the type of the device... \$\endgroup\$ – Mark Mar 20 at 6:12
  • \$\begingroup\$ No it means you have include the local heat from other parts to reduce the headroom to your max temp spec or add to the internal ambient. Or in other words add to the Rja of all parts from mutual coupling of heat. You verify this by testing. \$\endgroup\$ – Tony Stewart EE75 Mar 20 at 9:22

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