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I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in the Mealy machine the output depends on input and present state. But I don't understand how this could vary the number of states?

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    \$\begingroup\$ It's probably best if you set about studying one particular example that has been done up using both methods. But in general, you should be able to see that if you are allowed to combine transitions with states that you can get a higher output-state/machine-state ratio. \$\endgroup\$
    – jonk
    Mar 20 at 0:07
  • \$\begingroup\$ Yes in other words combining the present state with input and transition polarity increases the entropy of information added which both permit more complex but fewer states to realize. \$\endgroup\$ Mar 20 at 1:13
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If you're in state A and input X happens, how do you output Y?

A Moore machine must transition to state B whose sole purpose is to output Y, then back to A.

A Mealy machine can simply transition back to A whilst outputting Y

Thus a Moore machine requires more states. You need at least one state for every combination of outputs your machine requires.

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The more information or Bandwidth there is to determine the next state the fewer states or cycles that are required to complete the entire sequence.

This why DDR2,3,4,5,6,7,8 works faster by using transitions splitting the clock into N phases for parallel operations with N ports combined into 1. Thus the bandwidth is multiplied by the number of inputs added to the present state in this case split into equal phases.

By combining the present state with input you are adding more information and also entropy with the randomness of input states so when added with transitions and polarity of transitions, this extends the bandwidth greatly and allows more complex but fewer Mealy states to realize.

Complexity does not always mean hard to do, it just means more static and dynamic inputs with edge detection logic may be included to reduce the cycle time, latency or registers required.

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