# SAR ADC dynamic range and accuracy

This App Note states:

To have the maximum ADC conversion precision, it is preferable that the ADC dynamic range matches the maximum amplitude of the signal. Assume that the signal to be converted varies between 0 V to 2.5 V and that VAREF is equal to 3.3 V. The maximum signal value converted by the ADC is 3102 (2.5 V) as shown in Figure 9. In this case, there are 993 unused transitions (4095 – 3102 = 993). This implies a loss in the converted signal accuracy especially if the ADC lineaty performance is not ideal.

In my case I'm using a SAR ADC to measure RMS of sine wave. The ADC VREF is 3.3V coming from the same power supply of the microcontroller. The mid point of the input signal is set to 1.65V using the circuit below.

With 1.65V being the mid point, my RMS measurements have around 7% error.

When I use 1.25V as the midpoint as below, the error is reduced to ~1%.

The point is that I was expecting the error to increase with 1.25V mid point since the unused ADC translation range increased as my VREF remained to be 3.3V. Why is this?

• I expect the quantization noise (which is what's affected by this) is comparatively very small compared to other sources of noise in your system, but I haven't done any actual analysis. Commented Mar 21, 2021 at 20:43
• I'd like to see the exact algorithm you use to compute the RMS value. Also, have you fully apprehended the concept of DNL as it may apply here?
– jonk
Commented Mar 21, 2021 at 20:43
• Welcome Ander! Two suggestions: 1) in your 1.65 V example, you are using the raw 3V3 to derive the output whereas for the 1.25 V case, you are using a regulator - this could well affect your measurements. Try using the same for the 1.65 V example. 2) SAR DACs can behave non-linearly at the very low/high codes, so you should leave a little (5-10%) headroom at the bottom/top. Commented Mar 21, 2021 at 20:46
• @jonk I've reading a bit on the DNL error that may be caused near mid-range. Also found this post interesting. electronics.stackexchange.com/questions/335722/… Commented Mar 21, 2021 at 20:51
• @AnderCash Good stuff there I'd forgotten to also mention, with respect to sampling. That said, I still want to see your exact algorithm.
– jonk
Commented Mar 21, 2021 at 20:54

I was expecting the error to increase with 1.25V mid point since the unused ADC translation range increased as my VREF remained to be 3.3V. Why is this?

Simple:

Your 1.25V is stable because it is a lowish noise voltage reference, and it is not disturbed by current being pulled from it since it is only connected to the input of an opamp.

The 3V3 supply voltage is very noisy because it is the output of a voltage regulator of unknown noise, accuracy, drift, and output impedance, which supplies random varying current to the microcontroller. When the microcontroller draws more current, your 3V3 will drop a bit. When the microcontroller does something that requires less current, 3V3 will spike up. The regulator will do its job and keep it within tolerance so the micro does not crash, but there will be ripple and noise.

The output of an ADC is the ratio between the analog input value and the analog reference voltage. If the reference voltage is noisy, unstable, or inaccurate, then garbage in, garbage out.

So I think you assumed the "3V3" rail was constant voltage, it is not if a load draws varying current from it, like a microcontroller does.

Also, microcontroller ADCs are usually of the SAR variety. This is nice because SAR is very good at sampling, so you can sample a voltage exactly at the point in time you want. But unlike a sigma delta ADC, it does no averaging, which would average out the noise on signal and reference.

If you need accurate ADC readings, then you need an ADC reference voltage with the same level of accuracy. There are many voltage reference chips available with a choice of output voltage that will solve your problem, and most come with an internal opamp buffering the reference, so you can also simplify the circuit by removing the opamp. If you need a lower noise reference, or better temperature stability, make sure to check the specifications, and/or add filter capacitors on the output.

The Signal RMS= RMS (DC+Signal) - averaged DC value so the DC cancels out.

Non-linearity may occur with lost codes or “dead codes” and hysteresis caused by Vref crosstalk from the digital binary switched current e.g. xxx01111 to xxx10000 and visa versa. OR analog ground shift when shared with logic current from 0V ref.

So ensure Analog ground and Vref are isolated from logic current.