# SPD I2c Address for DDR4 SODIMM

While designing DDR4 SODDIM schematic for a mini-pc motherboard, I understood that I need to set an address to Serial Presence Detect (SPD) EEPROM so the CPU can identify the memory.

While looking at a previous design at a project in my company, I noticed that 3 pull down resistors are equal to the address A0. and someone wrote (0x50).

(NOP means Not Populated Resistor)

I'm trying to understand how to find these addresses and the conversion between (0x50) to A0 and vice versa.

I'm not sure if this is relevant. personally I didn't get from it any information that I can link to the previous image. but I thought it could help the answer.

regarding the last answers, I still don't understand how these addresses correspond with the outside resistors. actually I want to validate that the addresses are right. here is another example which makes the confusion, this image for the second SODDIMM slot in the design:

If you refer to the datasheet for an IC which could be used to implement the SPD feature, like a M34E04 from ST, you'll find that its 'base address' on the I2C/SMB bus has been set as 0x50 and that the 3 SAx pins are used to set the 3 least-significant bits of the address.

This corresponds to the table you found in the Micron app-note too.

When devices are addressed in an I2C/SMB bus, the 7 address bits are sent out first, followed by a single Read(0)/Write(1) bit.
So if you take the 1st 7 bits as 0x50 and shift them left 1 bit to add on a Read(0) bit, you get an 8-bit result of 0xA0.
If you instead use a Write(1) bit then you'd get 0xA1 instead.

Those 'outside resistors' in your schematic are connected to the SPD device's SA pins, so they set the address to which the SPD will respond on the bus.
In your 2nd schematic, those resistors feed values of 0, 1, 0 (0x02) to the 3 pins - so the SPD connected there will respond at address 0x52 (0x50 + 0x02), shifted left 1 bit and the Read/Write bit added on - so 0xA4 or 0xA5.

• Thanks for your answer. please see my question edit at the end, I'm still confused how these addresses correspond with the resistors outside. Commented Mar 22, 2021 at 17:35
• nice. so in this example I showed, I have two SODIMM slots, and both of them have an SPD EEPROM, where both could have addresses be set relative to 0x50? Commented Mar 22, 2021 at 17:52
• If you have more than 1 slot (and assuming that both slots share the same SMB bus for SPD), then the slots must have their address pin sets configured differently to each other - so slot 0 would be configured 000, slot 1 as 001, slot 2 as 010, etc. If you have 2 slots configured with the same address then your memory controller won't be able to differentiate between them. Commented Mar 22, 2021 at 17:56

0x50 in 7-bit notation which does not include the read/write bit equals 0xA0 and 0xA1 in 8-bit notation which does equal the read/write bit.

As each slot must have one address, and there are 3 address bits AD[2:0], you can set the address of a slot between 0x50 to 0x57.

• Thanks for your answer. please see my question edit at the end, I'm still confused how these addresses correspond with the resistors outside. Commented Mar 22, 2021 at 17:35
• nice. so in this example I showed, I have two SODIMM slots, and both of them have an SPD EEPROM, where both could have addresses be set relative to 0x50? Commented Mar 22, 2021 at 17:53
• Yes. This is important as when you know the slot address, slots can be on same bus and you can detect if a slot is empty or populated with a memory module. Commented Mar 22, 2021 at 17:55