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For my school project, I am designing a small PCB. For routing the signals I need to use a via. There will be around 500mA current flowing through the via. I am using 0.5mm traces to route the signals. At present, I have selected 0.75mm hole size and 1.35mm diameter for the via. Are these values okay? It might be a silly question but if someone could kindly explain to me what these two values actually represent and what's their significance?

Thank you

Hello, thank you very much for your reply. it was really helpful. I have a two-layer board and I have 35um copper both on the top and bottom layer. Regarding the plating thickness, isn't the bottleneck here the thickness of the copper within the via hole? I performed a check in the website:

http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/ .

I am attaching a screenshot here:

enter image description here

Here I have assumed the plating thickness to be 10um(very small) and it shows me the via has an estimated Ampacity of 1.74 amps. I might be missing something here and also my assumption of the plating thickness has been done by checking some other articles here in StackExchange. I would b highly glad if someone could kindly clarify if my estimation is correct.

Thank you again.

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  • \$\begingroup\$ For 500mA I'd suggest 4 vias in a group if you can afford the space. \$\endgroup\$
    – user16324
    Commented Mar 22, 2021 at 21:02

3 Answers 3

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In short/rule of thumb: If you are unsure that your via can carry the current you want, place more vias (more that you might need).

A short answer: Yes, it will able to carry the 500mA (But I think the via will get hot, so place a second via there as well)

The internal of a via: As you can see current flows on the walls of the via. If you fill the via with copper afterwards, it will be able to carry more current.

enter image description here

taken from here

Via filling example (blue is the copper fill, there is no solder mask (green) on this via so it is easier to be filled by you, the user/engineer):

enter image description here

Taken from here

You can see below, the "finished hole" is your 0.75mm hole and pad size is your diameter (1.35mm).

enter image description here

pic from here

You can calculate here how much current can pass through your via. You need one more information to calculate the current that can pass through the via. This is the Plating Thickness. This is the thickness of the copper on the top, bottom, in the vias and pads of the pcb. The via length is the length of your pcb.

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    \$\begingroup\$ Thank you for your reply :) \$\endgroup\$
    – zak3877
    Commented Mar 23, 2021 at 7:37
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The hole size is the drill size (with added thickness from the sidewall plating unaccounted for I think). The diameter is plated pad around the hole.

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    \$\begingroup\$ You can use the fab notes to tell the fab shop whether the hole diameters are intended as drill sizes or finish sizes. One place I worked would specify that sizes greater than 0.25 mm (IIRC) are finish sizes and sizes less than 0.25 mm are drill sizes (with plating tolerances that allowed them to be completely filled with plating). \$\endgroup\$
    – The Photon
    Commented Mar 23, 2021 at 0:22
  • \$\begingroup\$ In altium they are finished hole sizes. \$\endgroup\$
    – user57037
    Commented Mar 23, 2021 at 7:50
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The via pad (diameter) is the flat ring that goes around the hole to give the via some more strength and is where the tracks connect to (see the good images in the other answers).

In Altium, the via hole size is used to generate the drill diameter in fabrication outputs. In my experience, the board manufacturers take those diameters to mean the finished hole size, i.e. they increase the drill size then the plating will reduce the hole back to something close to the diameter shown in Altium. Plating is typically half the outer layer thickness, but you also have to account for drill tolerance.

Unfortunately, because Altium is using via hole as the drill size it doesn't allow for plating thickness, so this could cause clearance issues it can't detect. This is important if you run the "remove unused pad shapes" to trim the pad rings from vias on inner layers where there's no tracks. The DRC will then check clearance to Altium's 'hole', which is actually the finished size, and won't compensate for any over-drilling and plating thickness by the board house.

As The Photon mentioned, it's a good idea to add notes telling the board house how you want the sizes interpreted. Some might oversize the drills, others might not, so best to specify. Make sure your DRC rules account for plating and drill tolerance if specifying finished holes.

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