I'm making a CPU in which the memory is represented as a two-dimensional array, using FPGA. I've come to the implementation of registers, and I need the answer to this question. I'm new to electronics, and the answers I've seen were that it depends on the bus type: whether it's a single wire or their collection.

When I choose one, can you please give me a hint on implementing it in VHDL?

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    \$\begingroup\$ How would you possibly use serial registers in a CPU?? \$\endgroup\$
    – Hearth
    Mar 22, 2021 at 23:11
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    \$\begingroup\$ Depends on the CPU. Serial registers use fewer valves than parallel ones. But most CPUs since the early 1950s have used parallel registers. \$\endgroup\$
    – user16324
    Mar 22, 2021 at 23:15
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    \$\begingroup\$ @Hearth there are... specialized serial CPUs that have 1-bit wide data paths and 32bit instructions. github.com/olofk/serv (Olof is a funny guy. He uses this CPU to benchmark how mighty FPGAs ares: your FPGA's corescore is simply the number of RISC-V cores you can put on there) \$\endgroup\$ Mar 22, 2021 at 23:16
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    \$\begingroup\$ @MarcusMüller The problem is I'm new to VHDL as well and I counld't find a single example of exactly parallel register. I know that there are subcategories of serial registers, depending on their inputs and outputs (parallel in, parallel out; serial in, parallel out, etc). What to do? \$\endgroup\$ Mar 22, 2021 at 23:22
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    \$\begingroup\$ Maybe take a look at: freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/…. It is a great open book to start. \$\endgroup\$
    – devnull
    Mar 22, 2021 at 23:28

1 Answer 1


Not sure where you're coming from with respect to 'serial' registers. Generally, in a CPU nowadays these will be parallel, and usually some multiple of the machine's natural word width.

As to how you implement them...

Within a CPU, the local register set will be designed for low latency and for speed. This structure is sometimes called a register file, and it may have multiple read and write ports to support fast access to multiple operands at once. It may very well be constructed from D flops or latches, and also have bypass logic for when the read and write pointers are the same to eliminate an extra cycle of latency.

Bigger memories would tend to use FPGA RAM resources rather than D flops. The FPGA libraries offer different options for implementing RAM, including block RAM or distributed RAM (that is, repurposed LUTs), or honest-to-dog registers like for register files.

These RAM types are most easily used as parameterized macros, with synthesis taking care of the rest. Your tool chain offers various ways to make the instantiation templates. In Vivado for example, you can create the RAM as a GUI block design, then instance that in your code using the generated VHDL template for it. If you're relatively new to HDL coding this is an easy way to go.


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