Like in this example Common drain stage/Source follower circuit analysis there are many MOSFET push-pull circuits that show n-channel MOSFET on high-side position and p-channel MOSFET on low-side position being connected through their source connectors.
From testing a circuit with p-channel MOSFET on high-side and n-channel on low-side position (gate -> 10K -> GND), connected through their drain connector, my experience was, this would be a more stable and reliable circuit (on 5V VCC and 5V/0V gate voltages). (Example circuit for this complementary MOSFETs (P/N) circuit would be https://en.wikipedia.org/wiki/File:CMOS_inverter.svg)

What are difficulties with MOSFET source pins connected first version on biasing and why are drain connected MOSFETs not recommended (https://stackoverflow.com/questions/39116524/why-push-pull-can-not-work-in-this-manner - similar, but no explanation for MOSFET circuit) for power push-pull tasks?

  • \$\begingroup\$ Oh hold on. I think I completely misinterpreted your question. I thought your question was why do we sometimes use NMOS on the high side and NMOS on the low side isntead of always using PMOS on the high side and NMOS on the low side. But it seems your question is actually why NMOS on the highside and PMOS on the low side instead of PMOS on the high side and NMOS on the low side. So I have deleted my answer. \$\endgroup\$
    – DKNguyen
    Mar 23, 2021 at 4:56
  • \$\begingroup\$ Thx @DKNguyen for answer and comments. Did edit the question header for emphasising difference to common usage of n-channel, p-channel MOSFETs more clearly. Thanks for Your helpful input, looking at this difficulty from different viewing points (especially that biasing item). \$\endgroup\$
    – beyondtime
    Mar 23, 2021 at 5:02
  • \$\begingroup\$ From testing a circuit with p-channel MOSFET on high-side and n-channel on low-side position (gate -> 10K -> GND), Error: text to schematic parser currently broken, please include a schematic. What are difficulties with MOSFET source pins connected first version on biasing Error: text to schematic parser currently broken, please include a schematic. There is a schematic editor that's easy to use so USE IT. \$\endgroup\$ Mar 23, 2021 at 9:46
  • \$\begingroup\$ Because that allows both devices to be source followers. \$\endgroup\$ Mar 23, 2021 at 14:14
  • \$\begingroup\$ @Bimpelrekkie It's nothing more than a pull-down resistor to input gate for biasing NMOS (enhanced-mode) to defined high-resistance on Vds without sufficient gate input voltage level (breadboard and soldering took quite some time, but enabled measuring gate charges also: conclusion is, that (non-professional) voltage metering could add up to ~109% error, being 480nC instead of 230nC, plus additional losses on driving circuit previously to power MOSFET) \$\endgroup\$
    – beyondtime
    Mar 25, 2021 at 8:13

3 Answers 3


enter image description here

Right: common drain, push pull, source follower

This simple circuit with a NMOS and a PMOS is quite common. Being a follower, it has gain close to unity.

Switching applications: this is almost never used because to make the output swing to both rails, you need the NMOS gate to be driven higher than the power supply, and the PMOS gate to be driven to a negative voltage, which would add extra complication for no benefit. Also, in buck converter applications, when the output voltage is lower than half the input voltage then you want the lower FET with lower RdsON (so it should be NMOS) since it will be on most of the time.

Linear application: this is your standard follower output stage. It is easy to bias into classes AB or A or B, has high input impedance, it's pretty good. However if the drive voltage can't go above or below the power supply, then the output can't swing closer to the rails than one FET threshold voltage. If zero threshold voltage FETs are available (or JFETs) then it can be close to rail to rail if the driving stage is. If it is implemented with discretes and components like large capacitors are available, the driver can be bootstrapped to the output and generate voltages above VCC and below GND, so it can be close to "rail to rail". However, capacitance of FETs increases massively when Vds gets close to zero, so while it is very fast when Vout is away from the rails, it gets pretty slow and crummy when Vout is close to VCC or GND. So you must compensate the whole loop for that.

Why do I emphasize rail to rail? CMOS opamps are popular at low power supply voltages when a rail to rail output is a very important feature to have, and you won't find this structure in these opamps.

Middle: Common source complimentary

Switching: This can have both FETs ON continuously (not at the same time of course) without needing any boosted supplies, which is convenient if you want a buck converter or any other switching circuit that can do 100% duty cycle. Also, if the output/input voltage ratio is low, the lower FET will be on most of the time, so a higher RdsON PMOS on top is less of a problem.

Linear: This is your typical CMOS opamp output stage. It is rail to rail, and that will work down to a pretty low supply voltage. However it is more complicated to drive than the simple follower on the right, because it has two inputs instead of one. To bias it in Class A-B-AB properly, the sum of both Vgs must be constant and thermally compensated. In the follower configuration this is easy because there is one bias source labeled "V8" connected to both gates. In common source configuration, the sum of V5 and V4 must be held constant. Likewise the follower is easy to drive: it has one input. The common source requires a circuit to split the input signal into two complimentary halves to drive each FET.

Left: two NMOS

Switching: Since NMOS are faster, have lower capacitance, lower RdsON, etc, than PMOS, this circuit generally gives best performance for switching if you care about speed, RdsON, or cost. However it requires a boosted supply for the top FET. If you don't need it to be on continuously, this means a bootstrap, but if you do it means a charge pump. Since bootstrap requires a "large" cap, it can't be done in an IC without external capacitor. A charge pump can be done in an IC without external cap, but its output current will be tiny, so if you need speed... you'll need a decoupling cap. This is not the case for the NMOS/PMOS common source, which can switch fast without any help.

Linear: Basically the same characteristics as the previous one, with the same drive complications, except it's more linear (due to both FETs being identical), the NMOS is faster than the PMOS, and it's not rail to rail unless the top driver has a boosted supply. So this can be used for discrete amps, but not in opamps.

Cross-conduction: All of them can have cross-conduction.

The common source stages will cross-conduct if the gate drive signals turn both FETs on, or if high dv/dt on the output, through Cds, pulls the gate of the FET that is supposed to be off in the direction that makes it turn on, and whatever circuit is in charge to keep Vgs=0V has too high output impedance.

The common drain stage will cross conduct too, when it comes out of clipping, if the gate resistors values are too high and the driver slew rate is too high. If you use bootstrapped drive to turn one FET fully on, it will have a much larger capacitance than the other. When it tries to come out of clipping, this means the FET that was off, which has high Vgs and thus low capacitance, will charge its gate much quicker than the other through the same value gate resistor, and they will both turn on for a brief moment every time it comes out of clipping. If this goes on for enough cycles, the FETs will blow.

Note the issue is the same with the other circuits in linear mode if they are used in rail to rail mode: the FET that is fully on turns off slowly, the other turns on quickly. BJTs have the same issue in common emitter if you let them go in saturation, they take forever to come out of it.

Other linear considerations:

The middle one (common source) is voltage in, current out, which means it is a transconductance stage. The transfer function is not Vout/Vin, but Iout/Vin instead. To get Vout/Vin, you must take into account the load impedance. If it is unknown when designing the circuit, then potential stability issues arise, so something needs to be done to keep the whole loop stable, either compensation or a HF load impedance stabilization (Zobel) network on the output. On top of that, it is inverting, which means at frequency low enough that the FETs still have gain, for constant AC output voltage you get a drive current proportional to frequency due to Miller effect through Cgd. Since Cgd depends heavily on Vds, and gm depends heavily on Id and Vgs, and transconductance when driven from a finite impedance is proportional to gm/Cgd your loop gain will be all over the place.

But when the FETs run out of gain due to all the drive current being sunk into Cgs and Cgs, all you have left is Cgd which pumps the drive signal into the output, which means... it stops being an inverter. It's just a cap between gate and drain. So you get a 180° phase shift, at a frequency that depends on which FET is ON and how close to the rail the output is. This absolutely needs to be taken into account for loop stability.

The follower is... a follower, so Vout/Vin is close to 1. This makes it simpler to compensate the whole loop. At high frequency, it also becomes a capacitor, but since it was not an inverter at low frequency, you don't get the 180° phase shift. Again, easier compensation.

With discrete FETs, lead inductance will also mess it all up.

The one on the left will switch between both modes depending on which transistor is on, if you make the mistake to think it is a follower.

Note the drive current for all these is the same (ignoring differences between NMOS and PMOS). If you want an output voltage V, the load will want a corresponding current I to reach it, which means the Vgs of both FETs have to be brought to the same value no matter how they are wired, which means the driver will have to provide the same current to charge Cgs and Cgd in all cases.

  • \$\begingroup\$ Thx @bobflux, if I understand correctly, circuits for input signal or biasing are important for including every of that push-pull circuit variants in Your picture. In principle (what could be a next question?), is there dv/dt value range that makes common source, complementary variant acceptable on single voltage input signal to highPMOS,lowNMOS switching tasks, combined with short circuit protected, adjustable current limit supply for push-pull stage? \$\endgroup\$
    – beyondtime
    Mar 25, 2021 at 9:24
  • \$\begingroup\$ high pmos low nmos with gates tied together will always have some cross conduction unless gate voltages are adjusted just right relative to supply voltage, it's OK for logic gate, not a good choice for power \$\endgroup\$
    – bobflux
    Mar 25, 2021 at 11:07

First, what's happening with the high side NMOS/low side PMOS:

You can think of the goal of the push pull is to copy the voltage from the input to the output with efficient current gain. Since the output is connected to the source of both MOSFETs, it's like it's checking "is the output bigger or smaller than the input?" If the output is smaller, then the NMOS attached to the high supply voltage turns on (VGS is positive and above threshold) and lets current flow from the high supply until the output voltage equals the input voltage (when properly biased). If the output is larger, then the PMOS is turned on (VGS is negative and more negative than threshold) allowing current to flow out from the output to ground until the output voltage equals the input.

What are the biasing concerns with source connected push pull? You lose Vth between input and output unless you bias it properly. Those diodes help do that in your circuit.

Why don't you use drain connected in a push pull configuration? Shoot through. If you are using it as an analog push pull, both MOSFETs will be on at the same time often, drawing a lot of current. If you are using a digital circuit, it could be fine, and you're making a CMOS inverter by connecting drains together.

  • \$\begingroup\$ Thx @KD9PDP, so within this question it was conclusion to me, that first example circuit is not recommendable (maybe even not functional) below ~7V - ~10V VCC depending on MOSFET types (and only for enhancement-mode (opposed to depletion-mode types) MOSFETs, but that are most common types anyway)? Given VCC current is limited and VCC below maximum Vgs, drain connected highPMOS,lowNMOS might be better solution on soft switching gate voltage rise dV/V without difficult biasing if VCC is not that stable? \$\endgroup\$
    – beyondtime
    Mar 23, 2021 at 5:08
  • \$\begingroup\$ I think the purpose of the first circuit is not to be a push pull amplifier, but to be a common source amplifier with a voltage controlled Rd that can be adjustable for a wide range if VCC, like you said. So you're right that you need a decently high VCC. \$\endgroup\$
    – KD9PDP
    Mar 23, 2021 at 12:26
  • \$\begingroup\$ Actually I may be confused. Which circuit is the circuit you call "the first circuit?" Could you add them to your question? You have three links, and there are two circuits at the first link, and the first circuit is not a push pull amplifier. Which one is the first one? \$\endgroup\$
    – KD9PDP
    Mar 23, 2021 at 12:42
  • \$\begingroup\$ left circuit (first link) is high side n-JFET and low side n-JFET (NJFET?) and my interest inside this is MOSFETs (2nd circuit) and testing otherwise CMOS-like (second link) push-pull circuit combined with op-amp comparator adds suitable functionality (for now) for getting better 'near supply voltages' approach (and therefore ~30% improved efficiency, compared to highPMOS,lowNMOS) \$\endgroup\$
    – beyondtime
    Mar 25, 2021 at 7:53

In switching applications, the circuit with PMOS on top and NMOS on bottom is more efficient and is used for things like motor drives. However, it suffers from shoot-through so either needs independent control of the PMOS and NMOS or additional circuitry, both of which add complexity.

In switching applications, the circuit with the NMOS on the top and the PMOS on the bottom does not suffer from shoot-through due to the fact that they act as a antagonistic source-followers. However, it is less efficient in that it can't pull the output as close to the voltage rails as the other configuration due to Vgs_th. I'm sure these are used elsewhere but I have only ever seen them used as gate drivers where you don't need something super efficient and don't want extra complexity and size since the gate driver circuit itself is already something you are adding that adds complexity and size and you don't want it to snowball.

But in linear applications (like amplifiers), which are non-switching, where you want to be able to output a voltage somewhere in the middle of the rails rather than close to the rails having the PMOS on the top and NMOS on the bottom guarantees shoot-through unless you independently control the MOSFETs (i.e. have a circuit that manually decides when the crossover is and only activates one of the transistors). And unlike switching applications, the shoot-through here isn't a transitory condition; that shoot-through holds as long as your signal needs to be at that mid-rail level, wastes power and generates heat.

But with a NMOS on top and PMOS on a bottom, the shoot-through takes care of itself and all you need to do is bias it properly to compensate for the Vgs_th to ensure a smooth crossover you can drive both transistors from a single signal source which is a lot simpler.

  • \$\begingroup\$ Thx @DKNguyen, rethinking took some time, with getting ~3.5V loss for Vgs_th VccNMOS_GndPMOS is limited on low Vcc supply voltages and without signal input high or low (first link MOSFET circuit from question) input voltage is below 0.5*Vcc and was above 0.3*Vcc for symmetric biasing on conservative 10K resistors and silicon diodes on ~12V Vcc and non-optimized p-type for n-type MOSFETs (means to avoid tristate logic HI-Z state, uncommon, so mentioning just in case). Not fully been understanding importance of biasing yet, so it's work in progress. \$\endgroup\$
    – beyondtime
    Mar 25, 2021 at 7:29

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.