6
\$\begingroup\$

May I ask your comments on the layout below? Specially the via under the MCP16322. The layout is still missing the connector for the in/out voltages, but would love to have your opinion at this point.

MCP16322

Added after I read the answers: So much thankful for the great answers below and made changes accordingly. Will you please let me know what you think. Please don't mind the unrouted test points. enter image description here

Iteration 3. Added after reading Abdullah's answer: I couldn't get rid of one of the two traces cutting thru the ground. Tried to make it shorter. Is it not good to have it go underneath the chip? enter image description here

Schematics: enter image description here

\$\endgroup\$
  • \$\begingroup\$ First of all, it would be great if you had supplied a schematic, secondly what is the layer stack-up? Blue for bottom layer and red for top layer? If so, why didn't you spread the ground plane to all over the board? Is this board going to be hand-assembled? \$\endgroup\$ – abdullah kahraman Jan 19 '13 at 18:23
  • \$\begingroup\$ Where's the layout? I don't see anything... \$\endgroup\$ – DrFriedParts Jan 19 '13 at 18:33
  • \$\begingroup\$ 2 layers, red is top. Thanks for suggesting spreading the ground plane all over. \$\endgroup\$ – lyassa Jan 19 '13 at 18:36
  • 3
    \$\begingroup\$ Now, there is a reason why the ground plane should be as solid as possible. The ground plane is actually a return plane. It is the return path for the signals. So, if power goes to somewhere, it will come back home one day. And for the switching power supplies, the path to home will be the same path that the power went. Check out this answer as an example and draw the signals and their return paths in Paint, and you will see that some of them cannot come back on the same path they went. Try to make them come back on the same path by removing obstacles. \$\endgroup\$ – abdullah kahraman Jan 19 '13 at 22:22
  • \$\begingroup\$ I recently posted some guidelines over on the Meta site regarding design review/feedback questions that may help you get more answers. The biggest one in your case would be to add the circuit schematic to your question to go with the layout. meta.electronics.stackexchange.com/a/2520/10157 \$\endgroup\$ – Joe Baker Jan 19 '13 at 23:16
2
\$\begingroup\$

No reason for such disparity in track width. They should not be that thin. Take a look on page 15 of the User's guide for the eval board for this device: http://ww1.microchip.com/downloads/en/DeviceDoc/52030a.pdf

You should basically duplicate that design as much as possible for best performance.

Usually the inductor needs wider traces to reduce parasitic resistance and ensure a high current capability

Also, don't allow any traces in wierd angles. Delete them and redo them.

\$\endgroup\$
  • \$\begingroup\$ your answer was quiet helpful. Thank you. Will you please have another look at my round 2. \$\endgroup\$ – lyassa Jan 19 '13 at 22:19
  • 1
    \$\begingroup\$ Looks a lot better but I still see some more possibility for you to make tracks larger in the sense that they cover more area. Look at the track connecting the inductor to the top of C3. All that can be done in one piece with some thermal relief. \$\endgroup\$ – Gustavo Litovsky Jan 20 '13 at 1:15
11
\$\begingroup\$

The grounding on this design is very important. To achieve a good grounding, one should create a ground return path so that the "power signals" come back to their source on the same path they go.

If we were to categorize these power signals, we could separate them into two groups. "Quiet" power signals and "Wild and Noisy" power signals. As I have tried to explain about the noisy power signals in this answer, these signals must be taken of great care. In a typical non-synchronous buck converter, these signals include the ones which have a big change in current or voltage in-between the two cycles of buck converter. Have a look at the drawing below;

enter image description here

As you can see wild signals are the ones which change color. These include the path that includes the diode, and also the path that includes the input capacitor and switch. In your configuration, which is a synchronous buck converter, everything is the same, except you change the diode with an another switch.

Luckily these switches are integrated in the chip you are using. So that should give a big relief when laying out the PCB.

Coming to your 3rd edition of the design, let's highlight these paths.

When the upper switch is ON, the power will come from the source, go to your input capacitors C1 and C2, and then go into Vin pins of the IC, which are 2,3 and 11. Then, the power will exit from pins 1, 12, 13 and 16 and go to the inductor, then it will go to the output capacitor and then to ground, and it will try to return back using the same path.

When the upper switch is OFF, there is energy stored in the inductor when the switch was ON, this power in the inductor start flowing from the inductor go to the output capacitor, go to ground, flow back to PGND pins of the IC which are 14 and 15, then it will exit the IC from the pins 1, 12, 13 and 16 then go back to its source, that is the inductor.

In the schematic you draw, here are the two states of the converter:

ON State:

enter image description here

OFF State:

enter image description here

In the PCB you laid out, here is the two states of the converter:

ON State:

enter image description here

OFF State:

enter image description here

I am very puzzled about the return paths of the signals here, so if anyone has an opinion, I would be glad to hear. But basically, assume that the return paths are right under the trace. If we assume that, then there is no obstacle on the way back to home.

What can be done?

I see that your design is very similar to the reference design on the 22nd page of the datasheet, except you have routed Cin differently. Also, you have routed R1's connection to the 3.3V rail differently. Connect R1 to 3.3V rail just like they did in the reference design. Then, you will have room to connect Cin to the IC with a shorter trace. I have tried to explain in below picture. You can increase the number of vias which will bring better (lower impedance) connections..

enter image description here

Good article from TI: http://www.ti.com/lit/an/snva054b/snva054b.pdf

Sorry for the unnecessarily long post.

\$\endgroup\$
1
\$\begingroup\$

To answer your specific question, it's a bad idea to put an ordinary via in the middle of a solderable pad. If the board is being assembled using reflow, the via will suck the solder away from the joint. Such vias need to be filled, either with copper or a higher-temperature solder that won't melt during reflow. Either way, this adds cost to the assembly process that could be avoided by engineering the PCB differently to begin with.

\$\endgroup\$
  • \$\begingroup\$ I just wanted to say, that some boards are so small, you can't afford not to use a via-in-pad. Sure, not this board, but it is not inherently some "bad", wasteful thing. I hear people complain about via-in-pad all the time, but it is just one of the many tools in the toolbox a PCB layout designer can utilize. \$\endgroup\$ – dext0rb Jan 19 '13 at 23:48
  • \$\begingroup\$ That's why I qualified it with "ordinary via". As I said, there are ways to do it, but at increased production cost. \$\endgroup\$ – Dave Tweed Jan 20 '13 at 0:13
1
\$\begingroup\$

Comments on your second iteration:

I would recommend one via to the ground plane for each of the ground pins of the controller.

Because they provide 2 PGND pins and only one SGND pins, I assume PGND is the one that will have the most current (but check the datasheet on this). Right now, all the return current from PGND has to go through the EP pad, and past the SGND pin to get to a via to the plane underneath. This is exactly the scenario they were trying to avoid by having distinct PGND and SGND pins.

If you need more space for extra vias connected to PGND, there's no reason you can push the net connected to pin 1 back up underneath the inductor.

\$\endgroup\$
1
\$\begingroup\$

Another improvement for Iteration 3.

Place C1 and C2 as close as possible (asac) to MCP16322. These are the decoupling capacitors for the U1. Avoid put vias and do not change the layer. (Ok. Maybe you can do it for connect pin 11 but not for 2 and 3.)

I agree with the proposal of @abdullah kahraman

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.