You seem to have bitten off quite a challenge as SDRAM interfacing is not the simplest thing in the world. That said, here is what I would be checking.
Edge rates The entire question here depends on this particular item.
If you look in the IBIS model for this device and search for the term
ramp you will find the following:
The typical rise time is about 1.18V in 215 picoseconds and this is the starting point to deciding just how the routing should be done. The typical fall time is a little bit different but not enough to matter for the purpose of this answer.
A full rise time (in a 3.3V system) will therefore be around 390 picoseconds.
My rule of thumb is that if the flight time of a signal (the amount of time it takes to propagate from source to destination) is greater than 1/10th of a rise / fall time then I need to consider transmission line effects.
The typical propagation speeds on FR-4 are about 160 picoseconds per inch (surface) to 175 picoseconds per inch (internal layers).
As 39 picoseconds is about 0.025 inches (most flavours of FR-4, surface, 0.59mm) then series terminators are going to be a must for the DQ group. There will be some capacitance that might slow the edge rate down, but very little - 1" of 4 thou / 100 micron track with a distance to plane of 4 thou / 100 micron is about 1.1pF
Note that this is completely independent of the clock rate; it is the typical rise time of the SDRAM output driver.
From the above, it is clear that you will need to apply transmission line rules to the routing.
As the driver impedance is apparently around 36 ohms (calculated from the
pullup table with the output driver at 2V), I would suggest using 60 ohm tracks and a 24 ohm series termination resistor for the DQ group.
I have not done the same analysis for the STM32 device that will be driving the address and control groups or for the data drivers during writes
Length match needs to be independently analysed and you will need to find the timing range of the controller (in the STM32) for that. The length matching required (in terms of how close the lengths must be matched within each group) depends on the parameters of both the controller (in the STM32) and the timings of the SDRAM.
For SDRAM, the control and address group is matched to the clock as is the data group but they may have different rules (data may need to be more tightly controlled than the control and address group for example).