I am a chemistry student and I am beginning to realize that I have fallen into a EE rabbit hole..

I am trying to create a PCB (digital audio delay unit) from a schematic which includes a SDRAM, this is due to the fact that the circuit is supposed to be controlled from an external clock source and because the SDRAM is supposed to store audio data/signals (sampling).

I read that any signal(s) above 50 MHz constitute a high-speed design, requiring special routing rules. The max clock frequency that the SDRAM can handle is 163 MHz.

This is an audio circuit and the specifications for the circuit state that the audio inputs and outputs ( rise and fall time = < 1us) can range from 0-24 kHz and that the sampling rate is at 48 kHz. It also states that the external clock input can track a signal ( normally below 50 Hz) up to 2kHz (i.e from a vco) and multiply it up to 16 kHz.

So my question is, do I need to route this sdram according to high-speed guidelines when it seemingly will never need to operate above 50MHz?

Any thoughts/comments wille be greatly appreciated.

A section of the schematic with the main mcu and the sdram

A section of the schematic with the main mcu and the sdram

First page of the datasheet

First page of the datasheet

Link to datasheet

  • 2
    \$\begingroup\$ You have a mix of capitals and lower case. It's Hz, capital H. k for kilo is lower case, and M for mega is uppercase. Running at slower clocks does help because your signal has more time to settle between clocks, but your signal edges are still going to be fast enough to accommodate 150MHz signals unless there is a way to control the skew so that's still going to be a problem because those fast edges are what cause all the reflections in the first place. \$\endgroup\$
    – DKNguyen
    Mar 24 at 3:54
  • \$\begingroup\$ How much delay you really need to begin with? 32 Mbytes of RAM can provide almost 3 minutes delay for 2 channel stereo sampled at 16 bits.per channel at a rate of 48 kHz. \$\endgroup\$
    – Justme
    Mar 24 at 5:23
  • 1
    \$\begingroup\$ Yes, but it shouldn't be too painful to do so. At 50MHz you have some slack, more if you don't need to pass someone else's EMC testing. \$\endgroup\$
    – pjc50
    Mar 24 at 9:57
  • \$\begingroup\$ @DKNguyen, thanks for the clarification. \$\endgroup\$
    – J.Doe
    Mar 24 at 10:23
  • \$\begingroup\$ @Justme, really? The specs for the circuit state "16-bit mode: Maximum of 2 minutes 54 seconds per channel (6m49.5s total)▪24-bit mode: Maximum of 1 minute 27 seconds per channel (2m54s total)". \$\endgroup\$
    – J.Doe
    Mar 24 at 10:27

First of all, biggest misconception: it's not only the signal frequency that determines the routing type but the edges too. You can get in trouble even with a megahertz or so if it is steep enough.

That being said there are many different objectives in high speed routing: you may do it for controlling impedance, differential transmission or simply to match delays.

Assuming SDR SDRAM, you only need to worry about delays. DDR SDRAM has special signal levels, need Vrefs and IIRC the clock is differential too. SDR SDRAM has simple LVCMOS signaling so it's more manageable.

Remember that the clock for SDRAM is something essential, it has a maximum frequency but often even a minimum frequency. I don't know if you could run, for example, a PC100 chip at a couple of MHz and hope it will work correctly.

The single most important rule for SDRAM is that the traces for the signal group should be exactly of the same length (tolerance is on the datasheet). At these frequencies the bits have a finite and measurable length on the copper (due to signal speed). The SDRAM samples the lines on the clock edges: if some bit is earlier or later (setup and hold times apply) it will not work correctly.

To ensure this a tecnique called serpentine routing or length compensation is applied: you simply add some zigzag line to lengthen it and match the other one. Luckily modern EDA tools do it semi-automatically.

I recommend to check the application notes of both your SDRAM chip and your controller (the STM32), they most probably contain the detailed rules and useful examples.

  • \$\begingroup\$ @ Thanks for the insight. How do I identify differential pairs (dp)? Are the clock signal the only dps? Have you read about the length tolerances in the sdram datasheet? I can't seem to find it anywhere. \$\endgroup\$
    – J.Doe
    Mar 24 at 10:43
  • 1
    \$\begingroup\$ SDR don't use differential pairs, but these are clearly marked in the datasheet of the relevant parts. As for the STM32 layout I don't use the parts (I could cite a Texas Instrument application note) but you can find some info here: pcbartists.com/design/embedded/stm32-sdram-pcb-layout it says: 0.15mm of unmatched length causes ~1ps of skew. 50ps of skew is acceptable in most STM32 SDRAM PCB layouts. With modern EDA tools it's not too difficult to reach even 0.2mm of matching \$\endgroup\$ Mar 24 at 11:56

You seem to have bitten off quite a challenge as SDRAM interfacing is not the simplest thing in the world. That said, here is what I would be checking.

Edge rates The entire question here depends on this particular item.

If you look in the IBIS model for this device and search for the term ramp you will find the following:

The typical rise time is about 1.18V in 215 picoseconds and this is the starting point to deciding just how the routing should be done. The typical fall time is a little bit different but not enough to matter for the purpose of this answer.

A full rise time (in a 3.3V system) will therefore be around 390 picoseconds.

My rule of thumb is that if the flight time of a signal (the amount of time it takes to propagate from source to destination) is greater than 1/10th of a rise / fall time then I need to consider transmission line effects.

The typical propagation speeds on FR-4 are about 160 picoseconds per inch (surface) to 175 picoseconds per inch (internal layers).

As 39 picoseconds is about 0.025 inches (most flavours of FR-4, surface, 0.59mm) then series terminators are going to be a must for the DQ group. There will be some capacitance that might slow the edge rate down, but very little - 1" of 4 thou / 100 micron track with a distance to plane of 4 thou / 100 micron is about 1.1pF

Note that this is completely independent of the clock rate; it is the typical rise time of the SDRAM output driver.

From the above, it is clear that you will need to apply transmission line rules to the routing.

As the driver impedance is apparently around 36 ohms (calculated from the pullup table with the output driver at 2V), I would suggest using 60 ohm tracks and a 24 ohm series termination resistor for the DQ group.

I have not done the same analysis for the STM32 device that will be driving the address and control groups or for the data drivers during writes

Length match needs to be independently analysed and you will need to find the timing range of the controller (in the STM32) for that. The length matching required (in terms of how close the lengths must be matched within each group) depends on the parameters of both the controller (in the STM32) and the timings of the SDRAM.

For SDRAM, the control and address group is matched to the clock as is the data group but they may have different rules (data may need to be more tightly controlled than the control and address group for example).

  • \$\begingroup\$ Thankyou for the insight. Where did you find the driver impendance, or how did you calculate this? Why is it then 60 ohm, to " be one the safe side"? When you say "Length match needs to be independently analysed" do you mean the lengths are different for the different respective signal groups? \$\endgroup\$
    – J.Doe
    Mar 24 at 11:16
  • 1
    \$\begingroup\$ I have updated the answer to address at least one of your concerns. \$\endgroup\$ Mar 24 at 11:56

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