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I've been having trouble with what should be a really simple Momentary-to-Latch D flip flop switch circuit.

D Flip Flop Circuit

Basically:

  • I want the momentary switch PUSH to set the CP (Clock Pulse) Pin Low and on toggle SYSPWR pin high and low
  • BMOUT = supply = 5V
  • R107 is to act as a pulldown so there is no undefined behaviour on the pin
  • R106 and C109 are a RC filter so there is no bouncing on the CP pin on low-to-high transition

What's Happening, when pressing the PUSH button:

  • D and !Q pin is staying high
  • Q pin is staying low

Ideas:

  • need a resistor between D and !Q pin
  • need a pullup on Q pin

Can anyone tell me why this isn't working?

Here is the datasheet and truth table:

Truth Table

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    \$\begingroup\$ Qbar is an output. It's the complement of the other output Q. D is an input. You are shorting them together. Try leaving Qbar unconnected. \$\endgroup\$ – tim Mar 24 at 15:35
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    \$\begingroup\$ @tim I think the OP wants the Q to toggle every time the button is pressed. In other words, the D value needs to be the complement of the current Q value. Leaving QBAR unconnected to D doesn't produce a useful circuit. \$\endgroup\$ – Elliot Alderson Mar 24 at 15:41
  • \$\begingroup\$ If Qbar is unconnected then there is no signal on input D, so then the clock pulse doesnt change the output Q. I want them connected together so that we turn the momentary pulse into a latched pulse \$\endgroup\$ – Sam Bucca Mar 24 at 15:42
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    \$\begingroup\$ One thing I notice is your clock rise time is very slow, RC = 10 ms \$\endgroup\$ – user28910 Mar 24 at 15:46
  • \$\begingroup\$ You first need to verify you can successfully pass the D value through the flip flip. So disconnect D from Qbar, then try clocking D through. Next tie D high, and try clocking D through again. \$\endgroup\$ – tim Mar 24 at 15:48
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You're operating the device outside its RECOMMENDED OPERATING CONDITIONS. Of course you're free to do that but this can lead to unspecified behavior.

In your case the "Input Rise and Fall Time" specification is being exceeded. For 5V operation the specification is 5 ns/V MAX. So you need to ensure that your CP input rises from 0 to (0.7 * Vcc) in (0.7 *5V) * 5 ns/V = 17.5 nS.

Your CP rising edge is WAY WAY slower than that. Adjust the R and C values to give you a more reasonable TC (time constant) and you should see it behave better.

Operating Conditions

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  • \$\begingroup\$ I removed C109 and changed R106 to 100R, this gave me a 27ns rise time, which is still outside the operating conditions, but much closer to 5ns which allowed the flip flop to operate correctly \$\endgroup\$ – Sam Bucca Mar 25 at 15:27
  • \$\begingroup\$ Often these sorts of specifications can be "stretched" since in most cases the manufacturer is using worst-case conditions. But be very careful exceeding parameters in a production situation. For a one-off project, it will usually be fine. \$\endgroup\$ – jwh20 Mar 25 at 15:36
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I suspect that the slow rising clock edge might cause timing problems. I suggest that you swap R106 and C109. That will give you a fast rising clock edge on the clock when the button is pressed. I think a slow falling edge is less likely to cause problems, because Q and Qbar won't be changing at the same time.

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    \$\begingroup\$ I think so too. The datasheet says max rise time is 5 °C which is of course a typo. In real life it should maybe be 5 ns/V. Anyway, an obvious violation of edge rate. \$\endgroup\$ – Justme Mar 24 at 16:32
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You need a better method of debouncing the switch than the RC.

The RC may be good enough if you insert a Schmitt trigger gate after the RC and before the clock input eg. SN74LVC1G17-Q1.

CMOS gates have poorly characterized analog parameters- the minimum hysteresis is 560mV and the maximum 1320mV, but if the bounce time of the switch is less than a few ms and you increase the resistor to 200K it will probably be reliable, and chances are pretty good it will (at least initially) work as-is with the added gate.

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