Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs?

E.g., is there a threshold energy level for a single photon or neutron to corrupt a bit? Or is this a result of larger amounts of lower-energy radiation over some critical period of time? Is that threshold a function of the RAM circuit feature sizes and/or voltage?


1 Answer 1


Transient bit errors can be caused by a single high energy particle that deposits enough energy into the capacitor that stores the SDRAM's data, a single bit. This energy deposition can cause the bit to flip.

This phenomenon is a function of technology (CMOS being the most commonly used for SDRAMs) and feature size (the smaller the capacitor that stores the bit, the smaller the charge on that cap and so the lower the amount of energy needed to flip the bit). It can also be influenced by package style, plastic vs ceramic, for example.

And yes, the susceptibility of a SDRAM cell to being flipped is related to the energy of the particle that hits it. The higher the particle energy, the greater the chance of an upset.

This is an example of a Single Event Upset, or SEU.

Long term radiation effects fall under the category of Total Ionizing Dose, or TID effects. These effects usually cause DC type of changes, such as increasing leakage currents and shifting operating point biases which over time cause the part to degrade or stop working altogether.

SEU effects can be mitigated by various forms of scrubbing and ECC.

TID mitigation means buying a part that is inherently more radiation tolerant/hard or adding shielding to the vehicle. Note that shielding generally does NOT help with SEUs.


The preceding discussion applies to individual bits/cells in a DRAM. But a DRAM consists of more than just the storage cells. A DRAM contains a lot of digital and analog circuitry that controls the writing and reading of data from the storage cells. An SEU to a critical part of this read/write circuitry can render the entire DRAM inoperable, faulting all the data that is stored. This type of fault needs to mitigated at the system level (i.e. system level EDC), not at the chip level.

  • \$\begingroup\$ It is interesting that the latest Xilinx FPGAs have a lower soft error rate even though they are on a smaller geometry process; See xilinx.com/support/documentation/user_guides/ug116.pdf and go to the 'soft error' section. \$\endgroup\$ Mar 26, 2021 at 8:51
  • \$\begingroup\$ Yes, they do. But that document talks about soft errors in FPGA configuration memory cells, which are more like a standard RAM than an SDRAM's capacitor storage mechanism. That discussion also applies to SEUs in flip flops and registers, but this was not the question posed by the OP. \$\endgroup\$
    – SteveSh
    Mar 26, 2021 at 11:29
  • \$\begingroup\$ @PeterSmith There are certain flip-flop circuits that are more resistant to SEU at the expense of using more transistors or a bit more silicon area. So, changing from a normal FF in one process node to an SEU-resistant FF in a smaller process node will actually yield a lower SEU cross-section. \$\endgroup\$ Mar 31, 2021 at 23:08
  • \$\begingroup\$ Agreed that there are process or circuit design techniques (TMR for one) that yield hardened flip flops, and that sometimes a smaller feature size actually provides greater SEU resistance. But again, OP's question was not about SEUs and flip flops in general. \$\endgroup\$
    – SteveSh
    Apr 1, 2021 at 0:02
  • \$\begingroup\$ @PeterSmith Smaller node size actually decreases the scattering cross section and while less energetic particles may cause a bit flip, the overall BER goes down with smaller node size for cosmic ray mediated bit errors because of the reduced cross section. Most of the cosmic ray particles that hit the earth surface directly are very high energy, occasionally you have decay showers from collisions in the atmosphere which may be lower energy and you might see an increased BER under those showers, but most cosmic rays are already enormously energetic and can cause BER at any node size. \$\endgroup\$
    – crasic
    Apr 1, 2021 at 0:41

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