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  1. We always consider the gate source voltage as this determines the Vgs,off. But how come the Vgd doesn't have the same effect? enter image description here

  2. Following from this (and more importantly) why can't we have a negative Vds for an n-channel JFET?? I get that we need to prevent forward biasing between the diode, but that only means that Vgs < 0 and Vgd < 0, it does not mean that Vds < 0!

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Most JFETs are symmetrical, and the source of an N-channel is defined by convention as the non-gate terminal with the lowest voltage. You can switch the gate and source terminals and get the same effect.

MOSFETS may be symmetrical, but due to differences in construction meant to improve their performance, most are not. There may be JFETS which are asymmetrical, but I haven't run across them personally.

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  • \$\begingroup\$ There is an open question I'm watching about what makes some JFETs asymmetrical: electronics.stackexchange.com/q/541739/66767 \$\endgroup\$ – Theodore Mar 25 at 20:38
  • \$\begingroup\$ Thanks. @cristol-polychronopolis Can you explain why, for N-channel, the source is defined by convention as the non-gate terminal with the lowest voltage?? Why does this convention swap for P-channel? \$\endgroup\$ – ThePhysicsOverthinker Mar 25 at 22:06
  • \$\begingroup\$ Lowering the voltage on the gate decreases the (N-)channel width, but doesn't completely pinch it off until the gate reaches a certain (negative) threshold relative to the channel. The entire channel must be above the gate voltage by some amount to achieve effective shutoff. The smallest difference will be between the gate and the lower of the two channel terminals. As such, that one is called the source, and the threshold is specified as Vgs(th). The convention is mirrored for P-channel devices, with the same logic applying. \$\endgroup\$ – Cristobol Polychronopolis Mar 26 at 20:33

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