Following from this (and more importantly) why can't we have a negative Vds for an n-channel JFET?? I get that we need to prevent forward biasing between the diode, but that only means that Vgs < 0 and Vgd < 0, it does not mean that Vds < 0!
Most JFETs are symmetrical, and the source of an N-channel is defined by convention as the non-gate terminal with the lowest voltage. You can switch the gate and source terminals and get the same effect.
MOSFETS may be symmetrical, but due to differences in construction meant to improve their performance, most are not. There may be JFETS which are asymmetrical, but I haven't run across them personally.