Are carry flags set even when we discard the carry in an arithmetic logic unit?

Question

Currently I am learning simple binary math for a microprocessors course and have a trivial question on signed addition in 2's complement notation.
My professor mentioned that when we substract two numbers (to be precise, addition with a negative number) a carry is generated which is not an error and which can be discarded. Some examples with 8-bit signed numbers could be as:

   1111 1111 (-1)       0010 1000 (+40) 
+  1111 1110 (-2)     + 1110 1100 (-20)
------------------    ------------------
 1 1111 1101 (-3)     1 0001 0100 (+20)        
 ^carry discarded     ^carry discarded

Now, a carry is generated, but it does not indicate an error as without it the result is correct and we discard it. My question is, how the arithmetic logic unit handles this, knowing that binary adders don't know about signed/unsigned numbers. And if we take a look at a simple Full Adder circuit, the carry generated from the most significant bit is directly transferred, so the carry flag should be set if there is a carry.
But then how does it work when we need to discard the carry? Wouldn't it cause problems in consecutive arithmetic operations where an operation's carry-out becomes the other's carry-in?

Answer 1

Here's an example of a simplified 4-bit adder/subtractor that supports ADD, ADC, SUB, and SBB instructions:

(It doesn't include instructions to clear or set the CARRY flag. You'll just have to imagine that those also exist.)

The supported instructions are:

       ADD/SUB      ADC/SBB       CARRY-IN
ADD       0            0             0
ADC       0            1             C
SUB       1            0             1
SBB       1            1             C

I've added the last column above to tell you what the carry-in to the adder will be for each instruction. Where C is shown, the value comes from the result's carry-out of the prior operation. Otherwise, it's hard-coded to the value shown.

I want you to pay particular attention to this detail of how the carry-in is handled, because it's different from what you show. In the above diagram, you will see a mux used there, which either selects an opcode bit to pass along to the carry-in or else it grabs the carry flag that was stored in the prior operation.

Let's look at the six permutations adding two signed 4-bit values. (The carry-in is forced to 0 in this ADD case.) These are:

Take note of the carry and overflow status values, above.

We don't care, right now, about the ADC instruction. That will have to wait until later when we address multi-word operations.

There will be a similar set of six permutations for subtraction, as well.

Again, take note of the carry and overflow status values, above.

Now, of all the above there are four (two from the ADD group and two from the SUB group) where there was an overflow (V) set. Both pairs show a case where the CARRY is zero and a case where the CARRY is one. So this gives us a chance to see how multi-word operations take place where the CARRY value will be '0' in one case and '1' in the other. That should be good enough, I think.

So we have the following four cases where an overflow occurs (V=1):

  0000 0100 (4)      1111 1100 (-4)      0000 0100  (4)      1111 1100 (-4)
+ 0000 0101 (5)    + 1111 1011 (-5)    - 1111 1011 (-5)    - 0000 0101  (5)
-----------        -----------         -----------         -----------

I've keep these to just two 4-bit words above. But in the operations below, it's helpful to see it extended further. So I'll do that, below.

Let's start with the first case, 4+5. We already have the bits for the low order word from above. I'll then perform the high order word using ADC:

     STEP 1         STEP 2         STEP 3         STEP 4

          0 ADD          0 C            0 C            0 C
       0100           0000           0000           0000
 ADD   0101     ADC   0000     ADC   0000     ADC   0000
-----------     ----------     ----------     ----------
 0 1 0 1001     1 0 0 0000     1 0 0 0000     1 0 0 0000   ---> 0000 0000 0000 1001
 Z V C          Z V C          Z V C          Z V C 

That result is correct. It's 9 and there's no carry-out nor overflow. (The Z indicates a zero, which is not right for the double-word result. But it is right for the upper word.)

Next case:

     STEP 1         STEP 2         STEP 3         STEP 4

          0 ADD          1 C            1 C            1 C
       1100           1111           1111           1111
 ADD   1011     ADC   1111     ADC   1111     ADC   1111
-----------     ----------     ----------     ----------
 0 1 1 0111     0 0 1 1111     0 0 1 1111     0 0 1 1111   ---> 1111 1111 1111 0111
 Z V C          Z V C          Z V C          Z V C

That result is correct. It's -9. The carry of '1' in this case could be extended to still more words, if there were any.

Next case. Here, when reading the following keep in mind that the subtrahend is inverted before the addition takes place. A SUB operation sets the carry-in to '1', not '0'. A SBB operation leaves the carry-in alone -- to whatever was stored by the prior operation.

     STEP 1         STEP 2         STEP 3         STEP 4

          1 SUB          0 C            0 C            0 C
       0100           0000           0000           0000
 SUB   1011     SBB   1111     SBB   1111     SBB   1111
-----------     ----------     ----------     ----------
 0 1 0 1001     1 0 0 0000     1 0 0 0000     1 0 0 0000   ---> 0000 0000 0000 1001
 Z V C          Z V C          Z V C          Z V C

That result is correct. It's 9. The final carry is '0' which means there's a borrow if we were to continue extending the operation to additional words.

Finally, this:

     STEP 1         STEP 2         STEP 3         STEP 4

          1 SUB          1 C            1 C            1 C
       1100           1111           1111           1111
 SUB   0101     SBB   0000     SBB   0000     SBB   0000
-----------     ----------     ----------     ----------
 0 1 1 0111     0 0 1 1111     0 0 1 1111     0 0 1 1111   ---> 1111 1111 1111 0111
 Z V C          Z V C          Z V C          Z V C

That result is correct. It's -9. The final carry is '1' which means there's no further borrow if we were to continue extending the operation to additional words.

As another thing for you to consider when reading through the above extended word operations, please note that when an operation results in an overflow (V is set), then this means an extended word operation is required to take care of the issue. (If supported.) Once the V bit is cleared by an operation, there's no need to keep extending the size with added words. You can see that V=1 in STEP 1 of each case, indicating that another word operation is needed. But STEP 2 and beyond all have V=0. So that means no further extension is required and we didn't have to go all the way through STEP 4.

Answer 2

This depends entirely on what the processor architects decided to do with the carry. Remember that the processor won't know whether a carry will or will not occur, and won't know whether the operands are signed or unsigned, so it just does the same thing whenever it does an addition.

Perhaps a better way to think about this is that there will always be a carry out of the MSB during addition. Sometimes the value of the carry will be 0 and sometimes it will be 1.

Answer 3

Status bits are set/cleared by the processor depending on the result of an instruction execution. These status bits may or may not affect the execution of a subsequent instruction, it depends on the particular instruction. For example, processors have separate instructions for "add" and "add with carry"; the former is affected by the carry bit, the latter ignores it. The compiler will choose the appropriate instruction. For subtraction operations, the carry bit is regarded as a negated borrow