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Why, for an N-channel JFET, is the source terminal defined by convention as the non-gate terminal with the lowest voltage? Why does this convention swap for P-channel?

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  • \$\begingroup\$ This holds true for MOSFETs too. If you're sitting inside the MOSFET, which terminals are the electrons coming from for either device? \$\endgroup\$
    – DKNguyen
    Mar 25, 2021 at 22:55

2 Answers 2

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For an n channel J-fet it is the voltage between the gate and the lowest non-gate terminal which controls how hard the J-fet is turned on with the J-fet fully turned on when the gate voltage is equal to the voltage at the lowest non-gate terminal. Most J-fets are symmetrical and so, for a n channel j-fet, the lowest voltage non-gate terminal is defined as the source.

For an n channel J-fet the gate must be taken negative with respect to the lowest non-gate terminal to turn the J-fet off (depletion device) and the gate must not be taken much above the voltage at the lowest non-gate terminal or it will forward bias the gate diode.

Everything is reversed for P channel J-fets. It is the voltage between the gate and the highest non-gate terminal which controls how hard the J-fet is turned on with the J-fet fully turned on when the gate voltage is equal to the voltage at the highest non-gate terminal. Most J-fets are symmetrical and so, for a p-type J-fet, the highest voltage non-gate terminal is defined as the source.

For a p channel J-fet the gate must be taken positive with respect to the highest voltage non-gate terminal to turn the J-fet off and the gate must not be taken much below the voltage at the highest non-gate terminal or it will forward bias the gate diode.

The definition of the source as the lowest voltage non-gate terminal can cause distortion problems in ac applications such as wien oscillator gain control where the gate is held at a constant negative voltage with respect to one grounded non-gate terminal and the other non-gate terminal is oscillating about ground. This second oscillating, non-gate terminal will be the drain on positive swings and the source on negative swings and so the J-fet will be turned on more during negative swings (the gate voltage is closer to that of the source, the lowest voltage non-gate terminal) causing output distortion. A couple of high value resistors around the J-fet efficiently circumvents this problem.

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The "source" is the source of majority carriers, if I recall correctly. For NMOS the majority carriers are electrons, which flow from low voltage to high voltage. For PMOS the majority carriers are holes, which flow from high voltage to low voltage. So, the source is where the carriers enter the channel. After that they go to the...drain.

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