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I have three states in my mealey machine, when dcsel=0 then it goes to Grayscale state s1,if dcsel=1 then it goes to dot correction state s2,reset=1 then it stays in idle s0.I want to that in grayscale and dot correction state after delay of eightclock cycle it should generate signal without changing to other state.I mean generated enbale should be independent of state transition.Can i use task to call delay? I tried to use but i am doubtful whether it will work.

I have tried verilog code is

always @(dcsel or state or rst)
  case (state)

    idle: begin
      if (dcsel == 1'b1 & rst==1'b0 & hold_wr_dc == 1) begin
        // valid_wr_en  to enbale fifo to  write after 8 sclk
        next_state = dc;
        valid_wr_en <= 1;
      end else if (rst) begin
        next_state = idle;
        valid_wr_en = 0;
      end else if (dcsel==1'b0 & rst==1'b0 & hold_wr_gs == 1) begin
        next_state = gs;
        valid_wr_en =  1;
      end
    end

    gs: begin
      if (dcsel==1'b1 & rst==1'b0) begin
        next_state = dc;
        valid_wr_en = valid_en;
        valid_rd_en
      end else if(dcsel==1'b0 & rst==1'b0) begin
        next_state = gs;
        valid_wr_en = valid_en;
        valid_rd_en
      end else if(rst) begin
        next_state = idle;
        valid_wr_en = 1'bz;
        valid_rd_en
      end
    end

    dc: begin
      if (dcsel==1'b1 & rst==1'b0) begin
        next_state = dc;
        valid_wr_en = valid_en;
        valid_rd_en
      end else if(dcsel==1'b0 & rst==1'b0) begin
        next_state = gs;
        valid_wr_en = valid_en;
      end else if(rst) begin
        next_state = idle;
        valid_wr_en =  1'bz;
        valid_rd_en
      end // else: !if(dcsel)
    end
  endcase

always @(posedge sclk, posedge rst) begin
  if (rst)
    cnt <=0;
  else if(cnt != 'd8)
    cnt <= cnt +1;
  else if(cnt == 'd8)   // grayscale ,wait till 6 sclk to write in fifo
    hold_wr_gs < = 1;
  else if(cnt == 'd6)   // for dot correction wait till 8 sclk to write in fifo
     hold_wr_dc <=  1;
  else
    cnt <= 3'b0;
end
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  • 2
    \$\begingroup\$ This code has many syntax errors; fix those, and maybe someone will make the effort to try to figure out exactly what you're trying to accomplish here. \$\endgroup\$
    – Dave Tweed
    Jan 20 '13 at 14:41
  • \$\begingroup\$ Also, your English is very hard to follow. Please improve it. \$\endgroup\$
    – user17592
    Jan 20 '13 at 15:56
  • \$\begingroup\$ If you want an enable signal to go high every eight cycles, regardless of what state your state machine is in, simply make a second state machine (in this case, probably a 3-bit counter) to generate enable. You haven't said enough about the behavior you want to give you any more answer than this. \$\endgroup\$
    – The Photon
    Jan 20 '13 at 16:52
2
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There would be several ways to add the 8 clock delays. One way is to add a batch of new states to your state machine (basically add three more state bits) such that when you go from state to the next where the delay is desired you simply go as something like:

S3 -> S10 -> S11 -> S13 -> S14 -> S15 -> S16 -> S17 -> S0

Another way is to introduce an additional counter value that is handled outside the main state machine flops. Similar to above on the transition could look like this:

S3  ->  Sx ->  Sx ->  Sx ->  Sx ->  Sx ->  Sx ->  Sx ->  Sx  ->  S0
 cnt<-0   cnt++  cnt++  cnt++  cnt++  cnt++  cnt++  cnt++   cnt=7?
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