I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state.
The states are defined by a syntax similar to
type states is (s1, s2, s3);
Now, how do I build the units ports. What should I assign to it. Is it std_logic_vector or is it "states" type?
If I set std_logic_vector it says that the types are different and you cannot asssign.
If I use "states" it says that it cannot find this type. (because states is defined in its arhitecture)