# Statemachine as a separate module in VHDL?

I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state.

The states are defined by a syntax similar to type states is (s1, s2, s3);

Now, how do I build the units ports. What should I assign to it. Is it std_logic_vector or is it "states" type?

If I set std_logic_vector it says that the types are different and you cannot asssign.

If I use "states" it says that it cannot find this type. (because states is defined in its arhitecture)

You can define your type for the states in a VHDL package. Then include the package where your state machine is and in the file where you instantiation of that component is.

Another, but less beautiful, solution could be to assign in every state of the statemachine a value to a std_logic_vector output.

E.g.:

case current_s is
when s0 =>
....;
state <= x"00";
when s2 =>
....;
state <= x"01";
when s1 =>
....;
state <= x"02";


I would go for the first solution if your code is not shared with other designs or other people.

For IP's, I would go for the second solution. Some design rules will reject non standard input and outputs.

If you want to put the state into a debug register, the second solution will be the best (no problems with recoding of the states by the synthesis tool)

Put your state in a package. Alternatively, you can output a number related to the state on an integer port like this:

integer_port_name <= state_type'pos(state_variable_name);


The leftmost element of state_type will be numbered 0.