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I'm having a bit of trouble understanding how this logic level shift circuit works exactly. The design is from Sparkfun.
Hhere is the schematic:

enter image description here

For my application, the LV and HV are the 3.3V and 5V bus respectively. The LV1 and HV1 are the respective logic pins. I have a confident idea on how it works when LV1 is the input and HV1 is the output. However I can't seem to figure out how it works the other way around when HV1 is the input and LV1 is the output.

Here is what I know so far on how the circuit works. If LV1 is high, the voltage potential between LV1 and LV (gate of the N-MOSFET) aka Vgs is zero. Thus the MOSFET is off (open circuit) and HV1 only gets the 5V signal from HV through R4. When LV1 is low, there is a Vgs of 3.3V and the MOSFET turns on. From it, HV1 is at the same voltage potential as LV1 thus it's low.

Is my explanation correct on how the LV1 being the input works? How does the circuit work the other way around when HV1 is the input?

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  • \$\begingroup\$ The drain-substrate diode does the trick in that case. \$\endgroup\$
    – Mitu Raj
    Mar 26 at 19:29
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I can't seem to figure out how it works the other way around when HV1 is the input and LV1 is the output.

For my application, the LV and HV are the 3.3V and 5V bus respectively.

  • When HV1 is 5 volts, R3 dominates the LV1 terminal pulls it up to 3.3 volts. Q1 is off.

  • When HV1 is low it drags LV1 low via the bulk diode inside Q1. The action of doing that also turns on Q1 so that LV1 is close to 0 volts rather than 0.7 volts above it.

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  • \$\begingroup\$ I get the part on how HV1 pulls LV1 low now. Thank you for that but I'm still having trouble understanding the HV1 being high part. Let's say both LV1 and HV1 are low. Then the MOSFET is on. When HV1 goes to 5V, wouldn't it also go straight to LV1 through the MOSFET? \$\endgroup\$
    – Agriculex
    Mar 26 at 19:25
  • \$\begingroup\$ LV1 cannot be forced low when HV1 goes high because that node is connected to an input and therefore the 10 kohm pull-up dominates @Agriculex. In the process of HV1 being high and LV1 rising upwards, the MOSFET has to deactivate and that stops 5 volts appearing on LV1. \$\endgroup\$
    – Andy aka
    Mar 26 at 19:32
  • \$\begingroup\$ Oh...so the MOSFET starts to turn off the moment HV1 start to rise in voltage and fully closes before HV1 crosses the 3.3V threshold? Now it all makes sense now! Thank you! \$\endgroup\$
    – Agriculex
    Mar 26 at 19:40
  • \$\begingroup\$ It starts to turn off the moment HV1 begins to rise - just about but, be aware that this part of the switching operation is a little bit lethargic due to it now relying on the 10 kohm pull-up being dominant so, any input capacitance on LV1 will slow it down. \$\endgroup\$
    – Andy aka
    Mar 26 at 19:43
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When HV1 is the input- if HV1 is high then LV1 is high. Should be obvious.

When HV1 is pulled low, then the body diode conducts pulling LV1 down to about 0.7V. That puts about 2.6V on the MOSFET G-S, and it turns on, driving Vds down to about zero, and pulling LV1 down to almost zero.

Simulation in LTspice:

enter image description here

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  • \$\begingroup\$ I thought about it a bit more. Let's say both HV1 and LV1 are 0V. Then the MOSFET is on and HV1 and LV1 are connected. When HV1 goes to 5V, wouldn't LV1 go to 5V as well for a short amount of time before the MOSFET turn off from the drop in voltage potential between LV1 and HV1? \$\endgroup\$
    – Agriculex
    Mar 26 at 19:35
  • \$\begingroup\$ No, the MOSFET turns off quickly, and actually the rise time to 3.3V via the 10K pullup is rather lethargic. Even more so with a realistic input capacitance. I'll post a simulation. \$\endgroup\$ Mar 26 at 19:40
  • \$\begingroup\$ I see now. The MOSFET fully turns off when HV1 reaches the 3.3V threshold while going from 0V to 5V. Thanks a lot! \$\endgroup\$
    – Agriculex
    Mar 26 at 19:43

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