I need to convert a bunch of data signals from an FPGA coming out at 3.3V CMOS into 2.5V for an LCD display. I've found the SN74CB3T16210 and the SN74AVCBH164245 and they both seem like they'll do the job, but I'm worried about the clock line. I have a pixel clock running at around 10MHz that also needs to be level shifted and I'm worried that it won't come out clean.

Is the clock actually going to be a problem with either of these solutions?

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    \$\begingroup\$ I know that for SPI for 5V to 3.3V just voltage divisors of two resistors are used. You can see it here. That's lower speed however I believe, but you might just test this with your speed. \$\endgroup\$
    – user17592
    Jan 20, 2013 at 20:43
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    \$\begingroup\$ Takea look at the rating of the level translators and if they can support it. More important than the frequency is the rise and fall time. \$\endgroup\$ Jan 20, 2013 at 21:01
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    \$\begingroup\$ Please place links to associated devices you are using in the question, it is very useful to our members if they can just click and open the datasheet for your product. \$\endgroup\$
    – Kortuk
    Jan 20, 2013 at 21:34
  • \$\begingroup\$ Also, it would be helpful to explain exactly what you mean by "level shifted"? What are the final V_hi and V_low levels you need? \$\endgroup\$
    – The Photon
    Jan 20, 2013 at 22:17

1 Answer 1


When you say you need to "level shift" the clock line, do you just mean its one more line to convert between 3.3 V logic and 2.5 V logic? Or do you mean you need this line to have non-standard levels at the output (like V_hi = 2.5 V, V_low = 1.25 V or something)?

If you just need to convert to 2.5 V CMOS levels, almost any discrete logic technology that does 2.5 V ought to be able to handle 10 MHz clocks with no problem. For example, the SN74AVCBH164245 you mentioned specifies a maximum propagation delay of 3.7 ns when translating from 3.3 V (on the "A" side) to 2.5 V (on the "B" side). This is less than 5% of your 100 ns clock period.

As Gustavo pointed out in the comments, you also need to look at the rise and fall time of your signals. You need to work this out from the drive current available from your translating buffer (about 8 mA for the '164245 at 2.5 V) and the capacitance it's loaded with. You can roughly estimate

\$ t_{\mathrm{edge}} = \dfrac{\Delta{}V}{CI} \$

In this case you can have a load up to about 16 pF, and still be able to drive it over 2.5 V swing in about 5 ns, again much lower than your clock period.

As an aside, for one-way conversion from high voltage to low voltage, which it seems like you're doing with your clock, you can also look into using a 2.5 V buffer with "3.3-V-tolerant" inputs, for example SN74LVC1G34. This will be a slightly simpler and so probably a lower-cost solution.


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