I found a cool project (https://www.youtube.com/watch?v=aGCcT7p0-wY&lc=) which I want to replicate.

This is the flow:

Analog camera
-> ADV7180 (it converts the video from NTSC or PAL to 8-bit BT.656 YCrCb 4:2:2)
-> BT656 decoder
-> YCrCb to RGB converter
-> Dual Clock FIFO
-> Dual Clock FIFO
-> VGA

Data flow

Before replicating this project, I would like to understand the flow, so my question is:

Why this guy is using two Dual clock FIFOs and the SDRAM ? What's the purpose of using them?

Thanks in advance.


2 Answers 2


The incoming video clock is asynchronous to the FPGA clock. That is why it needs synchronization between video pixel clock domain and FPGA clock domain. And it might make no sense to send video data to DRAM at one byte at a time but many bytes at a time, a FIFO makes perfect sense to transfer data in bursts of few bytes at a time.

The DRAM is required for a frame buffer, because video input and output rates are not synchronized, and even worse, they will have different frame rates. Not to mention deinterlacing. So you need to store a whole incoming frame at say 50 interlaced fields per second, take two fields and deinterlave them into progessive frame at a rate of 25Hz, and then output that frame at 60 Hz for the VGA monitor.


Well, you need to have some sort of buffer if you want to convert interleaved video (PAL,NTSC) to full-frame video (VGA) at full resolution.

That is the SDRAM. (I don't know what the project does, probably something else than just displaying PAL video on a VGA display, but you don't tell).

The SDRAM has to run at a higher clock frequency than your pixel clock is running at, because you need to gain some time somewhere for refresh cycles.

If two data clocks aren't running synchronously, you need to have some translation between these – that's what the Dual-Clock FIFOs are for.

Same on the output side.


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