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I'm trying to use this code but for some reason I am getting Error (10500): VHDL syntax error at QA4.vhd(43) near text "0"; expecting ")", or ","

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity Radar is
port(rin : in STD_LOGIC_VECTOR(7 downto 0);
        AngleCode : in STD_LOGIC_VECTOR(3 downto 0);
        xDist : out STD_LOGIC_VECTOR(7 downto 0);
        Warning : out STD_LOGIC_VECTOR(2 downto 0));
        
end entity Radar;

architecture behavior of Radar is

signal int_rin,rinby8,xDistUnsigned: unsigned(4 downto 0);
constant code0: std_logic_vector(3 downto 0) := "0000";
constant code1: std_logic_vector(3 downto 0) := "0001";
constant code2: std_logic_vector(3 downto 0) := "0010";
constant code3: std_logic_vector(3 downto 0) := "0011";
constant code4: std_logic_vector(3 downto 0) := "0100";
constant code5: std_logic_vector(3 downto 0) := "0101";
constant code6: std_logic_vector(3 downto 0) := "0110";
constant code7: std_logic_vector(3 downto 0) := "0111";
constant code8: std_logic_vector(3 downto 0) := "1000";




begin
int_rin <= '0'&unsigned(rin);
rinby8 <= shift_right(int_rin,3);
with AngleCode select
xDistUnsigned <= rinby8*0           when code0,
            rinby8          when code1,
            shift_left(rinby8,1) when code2,
            rinby8+shift_left(rinby8,1) when code3,
            shift_left(rinby8,2) when code4,
            rinby8+shift_left(rinby8,2) when code5,
            shift_left(rinby8,3) when code6,
            rinby8+shift_left(rinby8,3) when code7,
            int_rin when others;
            
            xDist <= std_logic_vector(XDistUnsigned(7 downt 0)) ;
            
            
        
Warning <= "111" when(xDist > 200) else
              "110" when(xDist > 150) else
              "100" when(xDist > 100) else
              "011" when(xDist > 50) else
              "010" when(xDist > 25) else
              "001" when(xDist > 5) else
              "000";
end architecture behavior;
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  • \$\begingroup\$ Thanks, Sam, for formatting this! @BigJ, only you can tell us which line line 43 is! That's where the error is. \$\endgroup\$ Mar 28, 2021 at 23:03
  • \$\begingroup\$ xDist <= std_logic_vector(XDistUnsigned(7 downt 0)) ; The reserved word downto is missing a '0' (a typo). There are some range violations. \$\endgroup\$
    – user8352
    Mar 29, 2021 at 4:56

1 Answer 1

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Your error message is:

Error (10500): VHDL syntax error at QA4.vhd(43) near text "0"; expecting ")", or ","

This is reporting that the error is detected when parsing line 43. The problem could be before that line, but not usually after it.

Counting the lines in your source, line 43 (where the error is detected) is:

xDist <= std_logic_vector(XDistUnsigned(7 downt 0)) ;

And there does seem to be a mistake there. I'm not a VHDL expert, but there seems to be a typo: Shouldn't downt be downto ?

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