I've noticed that "AP-NMI" is pulled high on several ARM SoC schematics, and it is pulled high by the real-time clock (RTC) voltage, which is an always-on power domain (battery backup). Why is this?
I've also noticed that without NMI being pulled high (no RTC battery), a given SoC (A64) might not wake up from a watchdog-initiated reset. Are they related?
Also, how beneficial is the external NMI permanently being held high?
Here are some example schematics:
NanoPi A64 (ref)
Banana Pi (ref)
A31 PAD (ref)
My best guess is that NMI always being high wakes up the ARISC / AR100 / R_INTC systems, but the actual process escapes me.