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I've noticed that "AP-NMI" is pulled high on several ARM SoC schematics, and it is pulled high by the real-time clock (RTC) voltage, which is an always-on power domain (battery backup). Why is this?

I've also noticed that without NMI being pulled high (no RTC battery), a given SoC (A64) might not wake up from a watchdog-initiated reset. Are they related?

Also, how beneficial is the external NMI permanently being held high?

Here are some example schematics:

NanoPi A64 (ref)

enter image description here

Banana Pi (ref)

enter image description here

A31 PAD (ref)

enter image description here

My best guess is that NMI always being high wakes up the ARISC / AR100 / R_INTC systems, but the actual process escapes me.

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The Non-Maskable Interrupt (NMI) being low (=active) means that the CPU takes an exception immediately. If you don't need that functionality, you tie it high so that doesn't happen.

The CPU will likely wake up fine if the NMI is active, but takes an NMI exception while it is still processing the wakeup (which also shows up as an exception), so the NMI handler runs before the wakeup has properly reinitialized the system.

The other interrupts are disabled ("masked") until the wakeup code enables them, but the NMI cannot be masked.

Unless there is a silicon error, you can probably write an NMI function that works, but it would need a lot of extra care, so external hardware that needs the CPU to wake up and handle an NMI immediately needs to sequence that correctly.

That is an unusual use case though, most people use NMIs only for hardware errors that are detected while the CPU is running.

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  • \$\begingroup\$ Nice! To make this answer perfect, would you mind adding something about "NMOS open drain" which I just discovered is important to this IRQ pin from the PMIC. \$\endgroup\$
    – Drakes
    Commented Mar 31, 2021 at 16:40
  • \$\begingroup\$ @Drakes, that seems a very disingenuous proposal. Why don't you edit this finding into your question instead or post this answer. \$\endgroup\$
    – TonyM
    Commented Mar 31, 2021 at 18:33
  • \$\begingroup\$ @Drakes, the "open-drain" isn't so much an aspect of the pin as of the net connected to it. Basically you'd have one pull-up resistor, and all the NMI sources connected to it are either high-impedance or pull to GND. The case where you only have a pull-up and nothing else is the case where you have no NMI sources. \$\endgroup\$
    – Simon Richter
    Commented Mar 31, 2021 at 20:17
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As mentioned by Simon Richter the NMI (Non Maskable Interrupt) is typically active low, and the circuit diagrams you've provided indicate this with the AP-NMI# symbol, the # being a variant meaning 'active low' or 'inverse'.

Depending on the Interrupt design of the processor the NMI may be level or edge triggered. If level triggered, then having the NMI not 'high' will present problems. It will mean that the only thing that can be executed is the NMI interrupt handler. Every time the NMI interrupt handler exits (or otherwise re-enables global interrupts) then the NMI will be triggered again. This will essentially result in normal application code never really getting a chance to execute.

Typically you would want to supply the pull-up supply rail for the NMI from something which will be active whenever the processor itself is active. As you note, this may not always be the RTC power rail (if missing the RTC battery).

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  • \$\begingroup\$ Since NMI can't be masked, I wonder if NMI must be edge-triggered. \$\endgroup\$
    – user20574
    Commented Mar 30, 2021 at 9:27
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    \$\begingroup\$ That will entirely depend on how the interrupt logic is designed inside the processor. Typically level triggered interrupts will still only be captured when interrupts are 'globally enabled'.. and this will depend on whether the processor supports nested interrupts also. There's not really a fixed 'Standard' on how interrupts shall be implemented in a processor (but there will be N+1 such standards... [insert xkcd reference here]) \$\endgroup\$
    – BevanWeiss
    Commented Mar 31, 2021 at 0:13
  • \$\begingroup\$ It turns out that IRQ pin is NMOS open-drain and needs to be pulled high normally. \$\endgroup\$
    – Drakes
    Commented Mar 31, 2021 at 16:42
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    \$\begingroup\$ NMOS open-drain is an OUTPUT type (there being three typical digital output types, open-drain/open-collector, open-source/open-emitter, totem-pole/push-pull). The NMI pin is an INPUT.. these are quite unrelated. The reason for the drivers of the NMI pin being open-drain is that often you will have more than one driver of this input... and open-drains are an easy way to do this. \$\endgroup\$
    – BevanWeiss
    Commented Apr 1, 2021 at 0:15
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    \$\begingroup\$ NMIs are typically edge-triggered, yes. There may be CPU implementations that implement a special CPU state, but that is technically not different from a masking mechanism, except it would exclude normal interrupt processing as well, so the CPU could not be left in this state for extended time sensibly. \$\endgroup\$
    – Simon Richter
    Commented Apr 4, 2021 at 19:57
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I simulated a board with 2 integrated circuits and with PCB traces' parasitic inductance L and capacitor C.

Parasitic inductance on-line calculations: https://chemandy.com/calculators/flat-wire-inductor-calculator.htm

The first integrated circuit (victim) has a CMOS input stage with an external pull-down resistor of 10 k. This input mimics the NMI input pin of a micro controller.

The second integrated circuit (noise source) draws pulsed currents from the power supply. Pulses last 1 nano second and draw 4 A from the power supply. It seems much but it isn't.

Local to both the integrated circuits I put a filter capacitor of 100 nF.

My simulation demonstrates that parasitic inductance L create voltage spikes up to 500 mV close to the ground signal of the victim integrated circuits.

I attached the maximum low-level input voltage data of ONSEMI 74HC04: it's 900 mV

We have 400 mV of noise margin that is too low.

Please note how I measure the voltage spikes: I put the negative probe of the scope, local to the ground signal of the the victim integrated circuits.

I also simulated the case where the NMI signal is pulled-high. There's a small ring of 10 mV on the VCC.

enter image description here

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enter image description here

enter image description here

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    \$\begingroup\$ Your assumed \$V_{IL}\$ is not universal to all 5V CMOS inputs, much less all CMOS logic inputs. If I am designing a processor with a dedicated, active-low input I can ratio the transistors to provide a better noise margin in either direction. And this doesn't seem to answer the original question at all: why is NMI pulled high? \$\endgroup\$
    – Elliot Alderson
    Commented Apr 1, 2021 at 11:43
  • \$\begingroup\$ NMI active low was introduced some time in the 70's where Silicon technology allowed to build RTL and TTL circuits only and noise margins where very important. Nobody changed NMI active high since then. My answer is correct. \$\endgroup\$
    – Enrico Migliore
    Commented Apr 1, 2021 at 12:02
  • \$\begingroup\$ But nobody asked "Why is NMI active low?" And while your answer may be correct it is not necessary relevant. \$\endgroup\$
    – Elliot Alderson
    Commented Apr 1, 2021 at 12:45
  • \$\begingroup\$ The question was "Why is NMI commonly pulled high on many ARM SoC schematics?". The answer is "NMI is pulled high since the '70s an all microprocessors because ground bounce is dangerous". I showed that in my answer. \$\endgroup\$
    – Enrico Migliore
    Commented Apr 1, 2021 at 12:55
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To answer your question:

NMI is less sensitive to noise, if pulled high. The problem is the parasitic inductance of the PCB traces of the GND signal.

NMI is more sensitive to noise, if pulled down. You might receive spurious interrupts.

NMI is pulled high by an external resistor on 99.9 % of processor since 1970.

It's not pulled low because of ground bounces that happens on all boards.

Wikipedia:

In electronic engineering, ground bounce is a phenomenon associated with transistor switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate.

If the PCB traces of the GND signal are not wide and if the switching current is high, than the parasitic inductance may generate a ground bounce.

VCC/VDD are kept stable by a voltage regulator. If you know in advance that a voltage sag might occur on VCC/VDD, than you can increase the resistor value R1 and may be add a 1 nF capacitor C1.

enter image description here

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    \$\begingroup\$ Doesn't "VCC bounce" happen at the same time as "ground bounce"? \$\endgroup\$
    – user20574
    Commented Mar 29, 2021 at 17:23
  • \$\begingroup\$ Read the Wikipedia link. \$\endgroup\$
    – Enrico Migliore
    Commented Mar 29, 2021 at 17:33
  • \$\begingroup\$ "Read the Wikipedia link" is not a reply. If you choose to write an answer, the site naturally expects you to explain it and justify your claim. \$\endgroup\$
    – TonyM
    Commented Mar 29, 2021 at 18:44
  • \$\begingroup\$ It turns out that IRQ pin is NMOS open-drain and needs to be pulled high normally. \$\endgroup\$
    – Drakes
    Commented Mar 31, 2021 at 16:43

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