I'm trying to build a full-bridge dc-dc converter, PWM signals are ok but drain-source waveform has some problems. Here is drain-source waveform with a proper pwm signal on gate. enter image description here

Then I decided to add a C snubber(100nF) across drain-source and waveform turned into this:

enter image description here

Is the voltage waveform in 2.pic is acceptable? or do I need to make changes? I'm very weak about snubbers, even I don't know which snubber to use or should I use a snubber? Or is there any other way to make this better?

  • 2
    \$\begingroup\$ Yeah, that's too long of a settling time. You'll want more dampening. The resistor is probably easier, so increase it. Or if you don't have one, add it in series. Bear in mind I'm not addressing your specific mosfet circuit (since I don't see it.) I'm just speaking in general terms, seeing this scope picture at bottom. \$\endgroup\$
    – jonk
    Mar 29 '21 at 19:33
  • 4
    \$\begingroup\$ Details, we need details like: a schematic, links to datasheets of used components, photo of the setup (to see if it is a small PCB or a breadboard with long wires). Have you read this Application report: ti.com/lit/ml/slua618a/slua618a.pdf?ts=1616986179923 (not all of this is relevant but the basics in the first chapters are). \$\endgroup\$ Mar 29 '21 at 19:40
  • 1
    \$\begingroup\$ We need the schematic. \$\endgroup\$
    – DKNguyen
    Mar 29 '21 at 20:13

A snubber is designed to suppress voltage spikes. In your first photo, you don't really show any spiking, so a snubber is not what you need.

It looks like the problem is insufficient gate current. There is a drain-gate capacitance in a MOSFET that is likely causing your problem. When you switch "on" and the gate threshold is reached, the drain voltage drops from a high voltage to the source voltage at a high rate of dV/dT. If your gate drive has a high output impedance, this change of drain voltage tends to drive your gate more negative through the drain-gate capacitance. Since the gate has just passed the threshold , it is driven back below the threshold and turns the MOSFET "off," as shown in your first photo. The drain voltage rises and the gate voltage continues to increase and then the MOSFET turns back "on." The same thing happens on the falling edge, except the polarities are reversed. In you first photo, this happens once on the rising edge and two or three times on the falling edge.

When you put a capacitance across the drain to source, the rise and fall times are slowed so that the coupling from through the drain-gate capacitance is reduced. However, your capacitor combined with your circuit's inductance forms a "tank" circuit with the characteristic decaying sinusoidal waveform on every edge, shown perfectly in the second photo.

To solve your problem you can put in a gate driver with high current capability that will override the coupling effect. Or you can try a FET with lower gate-drain capacitance (which usually means a higher "on" resistance). Or you could have a layout problem - make sure your traces between the gate driver and gate are short and fat. When done right your switching time will go down and your "on-off-on" issue will be solved. A capacitor across the drain-source is not usually a good idea; it just causes higher peak currents.

When you get this fixed, your switching time will decrease and your efficiency will go up. If you have inductance in the layout, and this causes voltage spiking, then you can consider a snubber.

Good luck!


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.