I write embedded software that runs on a single board computer running Linux and talking to FPGAs. I do not do FPGA design, so I'm at the edge of my knowledge with this question: how do I program an FPGA without JTAG?


At my previous employer, we had what folks called "chain flashable firmware" which meant once we had programmed it via JTAG one time, we could then forever after use software to update the FPGA's code, and next time it booted it would be running the new FPGA version. It took a couple minutes, but worked without issues (unless the power went down while you were running the update... then you were back to JTAG the next time around).

At my current employer, this "sounds crazy" to those who write FPGA code. Every time we have to update the firmware, we have to tear everything apart, connect to the JTAG headers, and burn the firmware. (Yes, I understand if we routed the JTAG headers to the outside we would have a much easier time... that's not what I'm asking here.)

I want to be able to do this via software, but don't know enough, and every time I search the web for "update FPGA without JTAG" or something like it, I get answers about consumer electronics devices and how to update them. Just not what I'm looking for.

To the best of my understanding, the FPGA code is simply loaded into flash or an EPROM or a CPLD of some sort via the JTAG header.

  1. What is the mechanism folks use to update firmware without JTAG?
  • Is it just a matter of writing to flash?
  • Do we have to include some IP Core into the firmware that allows it to write back out to the place it reads its program from?
  1. Is it a good idea to allow updating firmware without JTAG headers?
  • I don't have any issue with it, but some express reluctance. My view is if we can do it in software and save ourselves a ton of time and effort, let's do it.
  1. Is there a MicroSemi version of Xilinx's SelectMAP? I think this might be what I'm looking for.

  2. What am I not asking that I should have?

Note: according to this guys answer, this is totally doable, BUT in my case I must have the firmware up and running well before the software comes up, so I can't be dynamically loading the FPGA code from the software each time the FPGA boots. It needs to be stored in some memory the FPGA uses upon its boot up, not coming from software. The only time I want it to come from software is when I attempt to change what the FPGA sees upon it's next boot up.


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    \$\begingroup\$ The method will be very specific to the FPGA or CPLD you are using, so we can't go further without that. Please edit your question and add the manufacturer and specific part you are trying to In-System Programme (ISP), along with any FEPROM used to store the configuration file. \$\endgroup\$
    – TonyM
    Mar 29, 2021 at 21:25
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    \$\begingroup\$ @TonyM It's a MicroSemi ProAsic3. See microsemi.com/product-directory/fpgas/1690-proasic3 Knowing the proper terminology (ISP) may be enough for me. I'll keep reading up on it. Thanks! \$\endgroup\$
    – kmort
    Mar 29, 2021 at 21:30
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    \$\begingroup\$ @TonyM Okay, so the MicroSemi documentation says "Designers can perform remote in-system reprogramming to support future design iterations and field upgrades" which means this is totally possible. I think I have enough information now to push for what I need. Thanks! \$\endgroup\$
    – kmort
    Mar 29, 2021 at 21:53

3 Answers 3


If you want to program the FPGA directly, such as when you are doing development work, you will use JTAG.

If you want to program an FPGA that uses external memory (which was the norm until recently) then you need only program the external memory device (which generally have their own programming protocols not using JTAG) and then reset the FPGA so that it does a load from memory.

I suppose it possible, though I have never done it myself, to allocate part of the FPGA to implement a loader so that you can load it (partially at least) using a different protocol than JTAG and go from there but that would be entirely up to the developer of the system.

  • \$\begingroup\$ The more I think about it (this was a long time ago), I think it was something they built into the FPGAs themselves. There were a bunch in the system and they put them in a "chain" so they could program the next one down the line. \$\endgroup\$
    – kmort
    Mar 29, 2021 at 21:31
  • \$\begingroup\$ @kmort, yes, I've designed firmware with remote update. What's possible and how it's done depends on the part and on the architecture of the system it's in. \$\endgroup\$
    – TonyM
    Mar 29, 2021 at 21:35

Present (series 7) Xilinx FPGAs support a number of methods to load the bitstream:

  • Master-Serial configuration mode
  • Slave-Serial configuration mode
  • Master SelectMAP (parallel) configuration mode (x8 and x16)
  • Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)
  • JTAG/boundary-scan configuration mode
  • Master Serial Peripheral Interface (SPI) flash configuration mode (x1, x2, x4)
  • Master Byte Peripheral Interface (BPI) flash configuration mode (x8 and x16) using parallel NOR flash

From here: https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

All of the 'slave' modes can be implemented by a microcontroller, with the Slave-Serial requiring the fewest pins.

Large Virtex devices (Ultrascale) support a 'Tandem' mode which allows a small bitstream to be loaded first (e.g., from SPI), then the rest over a fast interface like PCIe.

It is also possible to use the Master SPI mode, then offer the capability to re-flash in system remotely by instancing a SPI interface in the design, that can take over the Flash SPI pins once configuration is done. More here: https://forums.xilinx.com/t5/FPGA-Configuration/SPI-Flash-reconfiguration-a-modest-proposal/td-p/947747

Now, what does Microsemi support? For Polarfire, a subset of what Xilinx supports, namely:

  • JTAG
  • Master SPI (with a multi-image use model, like SelectMap)
  • Slave SPI

So seems like you could support the Slave SPI mode for in-system reconfiguration, as well as JTAG for debug.

More here: https://www.microsemi.com/document-portal/doc_download/136523-ug0714-polarfire-fpga-programming-user-guide

From this list: https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/56758-soc/56827-silicon-user-s-guides

  • \$\begingroup\$ Op states Microsemi, not Xilinx. This is just a copy and paste from the Xilinx tech docs, just a big comment really, and not an answer to the question. Downvoting accordingly, I'm afraid. \$\endgroup\$
    – TonyM
    Mar 29, 2021 at 22:46

We also needed to update the firmware without opening the products. Now we use this remote programmer from FPGA Cores:

The programming is done over Ethernet and you need to add one of these Ethernet cores. It works very good and we can also do remote debugging.

We mostly use Artix from Xilinx.


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