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  • My goal is to generate microcontroller-driven PWM from -10V (low) to 50V (high).

  • The load is 50Ohm resistive and sensitive to voltage, reverse voltage -50V (even on PWM) can cause dielectric breakdown.

  • Single MOSFET does not allow this. After some searching I found this diagram:

schematic

Image source: Electronics Tutorials - Complementary MOSFET Motor Controller

However I have some doubts about this configuration:

  • My driving MCU output is 2kHz with extremely low duty (<1us high time). So one MOSFET will work much harder than the other MOSFET.
  • The gate is floating At some point on rising or falling edge, both MOSFET will be on, shorting V+ and V-.

schematic

simulate this circuit – Schematic created using CircuitLab

Will something like this work ? (with deadtime) ?

Thanks in advance.

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3 Answers 3

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To have this to work, you need to drive each MOSFET independently from the MCU and implement the dead-time, to avoid having both fets conducting at the same time.

A lot of MCU with Hardware PWM functions will have this functionality available.

At this frequency, you should use a gate driver, given your voltages are quite far from GND, you can look at an isolated MOSFET gate driver.

It might be a good idea to also add a fuse, or limit the power supply current.

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  • \$\begingroup\$ The MOSFET pair is logic-level gate, are you sure gate driver is needed ? \$\endgroup\$
    – 7E10FC9A
    Commented Apr 12, 2021 at 22:49
  • \$\begingroup\$ It depends on the gate capacitance, the switching frequency, and the current capability of your MCU. @7E10FC9A \$\endgroup\$
    – Damien
    Commented Apr 13, 2021 at 2:17
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This is not a good way to do this. You need a pause between the gate pulses (called 'dead time insertion') to avoid cross conduction (tolerated in CMOS logic but usually fatal in power stages).

The simple way is to use a dedicated half-bridge leg driver: most of these have the circuit inside and as a bonus you use two N-channel MOSFETs (which is better for many reasons).

The alternative would be to use two different PWM channels and do the dead time insertion in software (some MCU have 'advanced PWM' that can do that in the timer hardware, too). In any case the gate drive would be split.

As for the 'one will work more than the other', well, that's not really an issue, especially if you use both N-channel with a dedicated leg driver.

The only thing somewhat unconventional is the need for a negative drive for the low side: you drive will need to be grounded at -VDD and you'll need some kind of level translation. These days is simply more common to use a single supply and a full bridge, but your solution is good too, if you have a negative power rail.

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  • \$\begingroup\$ Thanks for the info ! Could you please provide an example of full bridge implementation ? I don't actually have negative rail, but I have a DC-DC inverter module to produce negative rail. \$\endgroup\$
    – 7E10FC9A
    Commented Mar 30, 2021 at 8:25
  • \$\begingroup\$ In that case a full bridge is way better. First item in the catalog, the TLE7181EM has a reference schematic in the datasheet (also explains deadtime and the bootstrap operation for the high side). Really, most power IC manufacturers do something for H bridges \$\endgroup\$ Commented Mar 30, 2021 at 10:31
  • \$\begingroup\$ H bridge looks symmetrical (same forward and reverse voltage). However I require asymmetric forward and reverse voltage (-10V 50V). \$\endgroup\$
    – 7E10FC9A
    Commented Mar 30, 2021 at 15:27
  • \$\begingroup\$ drive in forward at 100% and in reverse at 20% pwm, where's the problem? \$\endgroup\$ Commented Mar 31, 2021 at 6:10
  • \$\begingroup\$ The load is resistive and sensitive to voltage, reverse voltage -50V (even on PWM) can cause dielectric breakdown. \$\endgroup\$
    – 7E10FC9A
    Commented Mar 31, 2021 at 6:40
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What you propose requires -10V at the gate of M2 to turn it off, and +30V at the gate of M1 to turn that one off. This requires some level translation from a 0V or 5V/3.3V logic signal. You won't be able to drive those gates directly from the MCU.

Another reason you may not be able to drive them directly from the MCU is that your required switching speed could exceed the speed with which a standard logic output can charge and discharge the gate capacitances. That depends on the transistor model, but consider that power MOSFETs in particular can have gate capacitances of many nanofarads, and from a 10mA digital source, this could result in transitions in the microseconds, too long to obtain clean <1μs pulses across the load.

Whatever level translation scheme you employ, it will have to produce gate transitions well under 100ns, and you may find it easier to use commercial gate driver ICs to obtain that. It is complicated by the unusual gate voltages you will need to produce.

The full H-bridge idea has a couple of advantages. One is that you need two supplies of 30V and 10V which are both positive with respect to ground. This enables you to use a single supply (say 5V or 3.3V) logic system, and all level translations stay in the range 0V to 30V. It might look like this:

schematic

simulate this circuit – Schematic created using CircuitLab

The "gate drivers" are just modules that perform the functions of level translation and fast gate voltage transition. You will notice that the driver for M1 must have a 0V/30V output, since that particular transistor requires 30V at its gate, to be switched off. The other drivers can all have 0V/10V outputs.

In this configuration, all gate potentials will remain 0V or positive. With transistors M1 and M2 on, while the others are off, the left side of the load is held at +30V, and the right side is grounded. In the opposite state, where M3 and M4 are on, the right side of the load is at +10V, and the left side is grounded, and note that the polarity of voltage across the load is reversed.

The problem of shoot-through in this configuration only occurs if (M1 and M4), or if (M2 and M3), are switched on simultaneously (or their simultaneous state transitions overlap, causing them to both be partially conductive for a while). To avoid that, you might require some kind of dead-time control, inserting a short delay between switching one pair off before switching on the other.

There are of course commercial gate drivers that do dead-time insertion, and these exist for half bridge and full bridge configurations. They will also take care of level translation, between logic outputs of an MCU and the require gate potentials.

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