This design doesn't work because if the reads and writes are high in successive cycles(burst transfer), pulse synchronizer output will only output one pulse in destination clock domain. Am I correct?
If you want to use pulse synchronizers to keep read-write pointer/counters synchronized to the respective clock domains, there are overheads to keep in mind. Normally you want to continuously enqueue/dequeue data to/from a FIFO every clock cycle. Suppose you keep write signal high for say 2 clock cycles, you have to get 2 synchronized pulses or a two-cycle long pulse at the read-clock domain, which will then update the pointers and the FIFO works flawlessly. BUT unfortunately pulse synchronizers don't work like that.
Consider a simple toggle/pulse synchronizer like this: (credits: edn.com)
For this pulse synchronizer to work correctly, the output signal from flop-A has to be stable for a minimum time period such that there is at least one clock edge at destination clock that will sample the data correctly without metastability. This is because it's possible that the signal causes metastability in the first clock edge at flop-B1. After metastability, flop-B1 may settle to a wrong value, which is then propagated by rest of the flops. However if flop-A output signal remains stable until the next destination-clock edge, it is sure that the correct value is sampled at the second clock edge.
Suppose write-clock is very faster than read-clock. Say, you keep write signal asserted high for 2 successive clock cycles (as we discussed at the beginning). What happens is that flop-A output toggles for a single write-clock cycle, and it is never sure that this single-cycle pulse at flop-A is correctly synchronized to the read-clock because of metastability. May be this transition gets completely missed before any sampling clock edge arrives at read-clock. It is also possible that the '1' from flop-A was sampled so close to the read-clock edge and it settled to '0' after metastability. Then the sampled signal remains '0' in remaining read-clock cycles as well, because the flop-A's output signal has already de-asserted after one write-clock cycle. The result is that the you missed the pulse completely. So the write pointer/counter will not be updated at the read-clock domain, and thus the pointers goes out of sync at the two clock domains, and the functionality of the FIFO flaws.
Thus you can't really get full throughput if you design an Asynchronous FIFO using pulse synchronizers. You have to pulse write and read properly for successive data transfer with enough time-period between the pulses for the destination clock domain to correctly sample and update the pointers.
Suppose if I have a case where writes and reads are not continuous but are separated by fixed 2-3 cycles will this design work
From above discussion I guess it's already clear that there is a dependency on clock periods of read and write. Suppose read-clock is at 10 MHz and write-clock is 100 MHz, pulsing write every 2-3 clock cycles is not going to guarantee synchronization with read-clock domain. Pulsing write for one cycle generates an active-high strobe signal (at Flop-A) internally which has to be sampled and converted to pulse at read-clock. You need longer wait duration before you can pulse the next write and be absolutely sure that synchronization happened; in this it would be greater than the period of read-clock ie., \$> 10\$ write-clock cycles.