I prefer to have a picture first so here's one:
Source: that TI document linked in the question.
Both integer PLLs (non-fractional) and fractional PLLs will have harmonics in the VCO's signal \$F_{VCO}\$.
It is the task of the Loop Filter to prevent the reference frequency \$F_r\$ from feeding through to the VCO. However, there's only so much suppression that any filter can achieve so there will always be some small part of \$F_r\$ and its harmonics that do make it into the VCO.
Note that \$F_r\$ will generally be a square wave so its spectrum will be consisting of \$F_r\$ and many harmonics of \$F_r\$. All of those can make it into the VCO. As these harmonics signals enter the VCO via the tuning input, the harmonics will modulate the VCO's frequency resulting in harmonics around the VCO's output signal.
In a non-fractional PLL, will be fixed so in its locked state, all frequencies in the PLL will be harmonics of \$F_r\$.
Things get "worse" in a fractional PLL as in a fractional PLL, N isn't constant. Instead N will be switched between N and N + 1 with a certain duty cycle to achieve the desired division ratio to get the desired \$F_{VCO}\$.
Now, you get a mix of frequencies, suppose the switching between the division factor N and N + 1 is done in a certain sequence and that sequence influences what harmonic signals you get at the output of the frequency divider.
Example:
non fractional PLL:
\$F_r\$ = 1 MHz, N = 1000 so we get \$F_{VCO}\$ = 1000 MHz
In this situation the spurs are 1 MHz apart so there are harmonics at ..., 998, 999, 1001, 1002 MHz.
The next higher frequency is made when we use N = 1001:
\$F_r\$ = 1 MHz, N = 1001 so we get \$F_{VCO}\$ = 1001 MHz
Suppose we want \$F_{VCO}\$ = 1000.1 MHz, then we have to use a fractional PLL where we switch between N = 1000 and N = 1001.
If we make N = 1000 during 90% of the time and N = 1001 during 10% of the time then we will get the desired \$F_{VCO}\$ = 1000.1 MHz.
The fastest we can switch between N = 1000 and N = 1001 is \$F_r\$ / 1001 as we need to let the frequency divider finish its N = 1000 or N = 1001 "count".
I mean, the N divider needs to count to 1001, then count to 1000 for 9 times and then count to 1001, then 9 times 1000 etc...
That process uses a long cycle meaning a low frequency (roughly \$F_{VCO}\$ / (1000 * 10) = \$F_{VCO}\$ / 10.000 ).
Compare that to the non fractional PLL where we had harmonics at each \$F_{VCO}\$ / 1000. Now we get 10x more harmonics! We get a harmonic every 100 kHz instead of every 1 MHz.
Things get even worse if we want \$F_{VCO}\$ = 1000.01 MHz, do the calculation yourself and see what you get!
There are "more clever" and "more complex" ways to make a fractional PLL, I used the "classic" fractional PLL as an example as I think that makes things more clear. When you understand this, the benefits of more advanced PLLs also become easier to understand.
