I am currently laying out a space constrained PCB which contains some USB 3.0 Superspeed differential pairs. These USB signals are confined to the PCB, going from a Cypress CX3 chip to a USB 3.0 Hub chip. They do not go to or come from a connector. The signals are approximately 30mm long from start to end.

USB 3.0 differential pairs

According to the advice, the Superspeed pairs should be separated from each other by at least 5x the differential pair spacing. (This is known as the 5W rule)

Since the signals are fairly short, and do not go through a connector or cable, would it be possible to push them a little closer than 5W? Say, 4W or 3W?

  • \$\begingroup\$ How many layers do you have? if > 2, what's your stackup? \$\endgroup\$ Commented Mar 31, 2021 at 13:05
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    \$\begingroup\$ also, I honestly think you're really overdoing it on the length matching - if you don't do these extra meanders, yes, your traces will be mismatched in length by easily up to 2mm. I very much doubt you're controlling the the properties of your PCB and vias well enough to justify taking that much precaution about length matching, and surprise, the main E-field doesn't actually happen between the differential pair, but between each trace and ground (compare: distance and area – the average voltage difference between the differential pair isn't even 2× as high as from single trace to groundplane) \$\endgroup\$ Commented Mar 31, 2021 at 13:25
  • \$\begingroup\$ but by doing the meandering, you reduce distance, especially close to the chip on the right, to traces where you want to go away from as straight as possible. \$\endgroup\$ Commented Mar 31, 2021 at 13:26
  • \$\begingroup\$ @MarcusMüller - It's a 6-layer board. SGP - PGS. 0.11mm between outer layers. 0.99mm between the inner two power layers. \$\endgroup\$ Commented Mar 31, 2021 at 13:40
  • \$\begingroup\$ @MarcusMüller - It's hard to know about the length matching. On one hand, almost all of the datasheets and app notes stress the length matching very strongly. On the other hand, a lot of old, experienced PCB design engineers laugh at those app notes, and say it's not true. \$\endgroup\$ Commented Mar 31, 2021 at 13:45

1 Answer 1


The document you linked says this: -

enter image description here

Does that help you? Can you place ground between or can you route on different layers separated by a ground plane? See also section 7.2 of that document.

  • \$\begingroup\$ Doh! didn't see that next paragraph. Something wrong with my eyes. Sadly I have diff pairs on both sides already. Also, won't adding ground in between them alter the impedance? \$\endgroup\$ Commented Mar 31, 2021 at 10:06
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    \$\begingroup\$ Yes, it'll alter impedance and you'd have to compensate by changing the track widths. \$\endgroup\$
    – Andy aka
    Commented Mar 31, 2021 at 10:07
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    \$\begingroup\$ Coplanar Ground will reduce impedance and allow you to make the differential pair narrower to hit the target impedance - saving even more space. \$\endgroup\$
    – tobalt
    Commented Mar 31, 2021 at 10:18
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    \$\begingroup\$ I'll allow myself the remark that I do think the advice to put ground-fill in between is to be taken with a fair amount of skepticism. The 5W rule is to limit cross-talk. Violating that, you can get away if you add a very good ground plane in between these two, in hopes the E-fields will happen mostly between tracks and between tracks and the coplanar ground plane. However, especially in a crowded situation, you're very limited in how perfect a ground plane on the same layer can be – <5W isn't really that much space that you can have arbitrarily many vias! I'll venture a guess that this advice \$\endgroup\$ Commented Mar 31, 2021 at 13:00
  • \$\begingroup\$ is hand-me-down advice from a more civil age of lower frequency signals, and not the result of extensive simulation/modelling. (but: I have no simulation of my own, so I'll go away if someone actually says "I do have experience and this isn't right") \$\endgroup\$ Commented Mar 31, 2021 at 13:01

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