It is common wisdom that decoupling caps should be near the IC drawing power, minimizing loop inductance.
For some time, I have seen that Todd Hubing advocates what he calls global decoupling in some of the youtube examples they have for LearnEMC, if the board has a tightly spaced power and ground plane pair.
The rationale is, that - with tightly spaced power and ground planes - the inductance of the plane pair is anyway smaller then interconnect traces. So if the decoupling caps lowest impedance path is through the plane pair anyway, then it doesn't matter that much where on the plane the decoupling cap is placed. Here is one example screenshot from that video which illustrates the placement of the global decoupling caps.
As a result they advocate, just sprinkling the board with a sufficient number of decoupling caps. Yesterday, Altium posted a new youtube video with Todd Hubing where he also explains this approach. It sounds quite plausible.
However, I do not recall seeing this school of thought anywhere else and most designs do have the decoupling caps very close to ICs, although I suppose most designs on 4+ layer board do have tightly spaced power and ground areas. As Todd Hubing mentions, caps near the ICs can actually make the situation worse because routing can be more congested when caps are very close to ICs.
So I was interested if there are problems with global decoupling unmentioned by Todd Hunting, that explain why it is not used more often.