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It is common wisdom that decoupling caps should be near the IC drawing power, minimizing loop inductance.

For some time, I have seen that Todd Hubing advocates what he calls global decoupling in some of the youtube examples they have for LearnEMC, if the board has a tightly spaced power and ground plane pair.

The rationale is, that - with tightly spaced power and ground planes - the inductance of the plane pair is anyway smaller then interconnect traces. So if the decoupling caps lowest impedance path is through the plane pair anyway, then it doesn't matter that much where on the plane the decoupling cap is placed. Here is one example screenshot from that video which illustrates the placement of the global decoupling caps.

enter image description here

As a result they advocate, just sprinkling the board with a sufficient number of decoupling caps. Yesterday, Altium posted a new youtube video with Todd Hubing where he also explains this approach. It sounds quite plausible.

However, I do not recall seeing this school of thought anywhere else and most designs do have the decoupling caps very close to ICs, although I suppose most designs on 4+ layer board do have tightly spaced power and ground areas. As Todd Hubing mentions, caps near the ICs can actually make the situation worse because routing can be more congested when caps are very close to ICs.

So I was interested if there are problems with global decoupling unmentioned by Todd Hunting, that explain why it is not used more often.

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  • \$\begingroup\$ Opinion-based answers are off-topic on this site. Questions that have objective answers are preferred. Can you make this a more specific question? \$\endgroup\$ Mar 31, 2021 at 13:03
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    \$\begingroup\$ Thanks, Elliot. I have changed the last sentence to be an actual technical question. \$\endgroup\$
    – tobalt
    Mar 31, 2021 at 13:19
  • \$\begingroup\$ You can also do truly global decoupling with a dielectric plane in the stackup, the whole board becomes a huge capacitor. But local decoupling have the advantage of minimizing the inductance between the capacitor and the power pin. With HF circuits even some millimeters of copper is too much and arguably the via to the power plane has some inductance too. I think it would be feasible once you have the means to measure or simulate reliably the actual impedance between the supply and the vcc pin (that's what bypass capacitor are at the end of the day) \$\endgroup\$ Mar 31, 2021 at 14:18

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This is true IF the power and ground planes are tightly coupled. What do you get with two copper planes very close together but not touching? A capacitor. And yes, since the power/ground vias can drop right from the pins to the respective plane, the inductive loop is much smaller making that capacitance much more effective at higher frequencies where small capacitors have trouble.

You will however still need larger “bulk” capacitors (typically 10uF) around the ICs. These capacitors offset the resistance of the switching current path back to the power supply. They can already tolerate a bit more inductance as they target the lower switching frequency currents of the IC and don’t need to be right on the pins and can me optimized with lower priority than the signal trace fan-out from the IC.

Why isn’t this used more often?

  1. It requires significant space on two PCB layers that cannot be split with a routing trace through them. Splitting the trace will result in loop currents again introducing inductance again and radiated emissions.
  2. It requires two planes of the board around the IC. Not a problem if you have an expensive 8 or 12 layer PCB design. Go nuts :)
  3. Many complex ICs require multiple power supplies. Each supply will require its own power/ground plane around the IC which eats up more valuable routing planes around the IC. Again, not an issue on designs with large number of PCB layers.
  4. To keep costs down, the goal is often to reduce the number of layers in the PCB. If this can be done with optimized placement of decoupling capacitors, the cost will be less than introducing more layers into the board.

It all really comes down to trading off design time, complexity, and cost. The main point is that you need to evaluate your PCB power and ground along with your decoupling capacitors to effectively determine the impedance of the power distribution network. From there you can determine if it meets the requirements for the switching current frequencies of that particular IC.

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  • \$\begingroup\$ Good point about multiple power rails. This either quickly grows the number of layers or makes the intermingling power areas tedious to plan. \$\endgroup\$
    – tobalt
    Mar 31, 2021 at 13:56

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