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Inspired by the question Op amp Power supply splitter with totem pole I played with the buffered rail splitter in LTspice. I placed a current sink as load on the output to simulate the current sourcing and sinking of a connected amplifier with 100mA amplitude and 50Hz. The output is stable to 20µV, so everything is fine (Fig 1).

But when I increase the size from the bypass caps C1 and C2 at output (as one would do to bypass the supply on succeeding amplifier stages) the whole circuit starts to oscillate (Fig 2). For the screenshot I used values of 100u for C1 and C2, but even with 100n the circuit is already oscillating.

  1. What is the reason for this oscillation with some capacitance between the new ground and the symmetrical supply rails? I would have assumed these caps would even increase the stability, as the feedback to U1 is now somewhat low pass filtered.
  2. Can I compensate for that behaviour? How?

enter image description here Fig. 1: Stable buffered rail splitter

enter image description here Fig. 2: Oscillating rail splitter with bypass capacitors

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What is the reason for this oscillation with some capacitance between the new ground and the symmetrical supply rails? I would have assumed these caps would even increase the stability, as the feedback to U1 is now somewhat low pass filtered.

Just because you have buffered the op-amp with an emitter follower push-pull circuit does not mean you have somehow isolated the op-amp from oscillating when you close the feedback loop. Pretty much any op-amp will sing its little heart out when the loading capacitance rises to a certain value and might only stop singing when the capacitance has risen to an unfeasibly and not useful large value of thousands of micro farads.

Can I compensate for that behaviour? How?

You can stop it by slugging the op-amp response with a local integration capacitor from op-amp output to inverting input but, make sure you use a 1 kΩ to 10 kΩ resistor to connect the inverting input to the emitter follower output.

enter image description here

My answer to this question contains a detailed breakdown of why an op-amp (buffered or not) will sing when capacitance rises to a certain small value and why it won't stop oscillating until the loading capacitance reaches a much, much higher value.

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  • \$\begingroup\$ What is the Phase margin Andy? And Load regulation error? 2N3055 was chosen for this reason.(I suspect) \$\endgroup\$ – Tony Stewart EE75 Mar 31 at 13:43
  • \$\begingroup\$ The AD820 phase margin is about 50 degree Tony but that is unimportant and you should know why. \$\endgroup\$ – Andy aka Mar 31 at 13:46
  • \$\begingroup\$ I was not asking about this, rather the net result with changes and load \$\endgroup\$ – Tony Stewart EE75 Mar 31 at 13:51
  • \$\begingroup\$ Oh, that works. Some vague memories come up there. I think I can't follow your other answer completely yet, I have to refresh some never used theory first... But why isn't the opamp decoupled from the output capacitance by the low impedance follower stage in between? \$\endgroup\$ – jusaca Mar 31 at 14:43
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    \$\begingroup\$ The physical output pin of the op-amp is "decoupled" from the "new" output regards loading but, that "new" output becomes an extension of the op-amp's output - after all, you are using negative feedback from that point back to the op-amp and the push-pull stage is inside the loop and, anything inside that loop that deteriorates phase margin, will drive the circuit into oscillation at some point @jusaca \$\endgroup\$ – Andy aka Mar 31 at 14:57
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Short out D1,D2, and R1 And remove R4,R5 which are no longer needed.

To scope , increase the Sweep speed and show actual resonant f. It may include your wire jumper inductance if long if connected to remote large Cap.

  • if so then add a small choke in series from emitters for rated current of say 20mA x hFE
  • Add a cap across R3 to stabilize reference for some T=ReqC
  • You should then have a greater GBW but less compensated due to addition RC in feedback Cload/hFE * Rout/hFE (OpAmp=220 approx for BJT type)
  • Then show results with a step load. (BJT buffered)
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  • \$\begingroup\$ Why would you remove the biasing path for the tranistors? That should give some nasty spikes when the follower stage has to switch from one transistor to the other, shouldn't it? With the biasing path it is a smooth transition. \$\endgroup\$ – jusaca Mar 31 at 14:45
  • \$\begingroup\$ Not at all, the BW of the OA will correct for overshoot with the load and slew rate limiting. With 1e5 feedback gain. The SIMPLEST fix is to suppress all opportunities of Positive Feedback such the cap on Vin+. I recommended. PSRR is not enough. \$\endgroup\$ – Tony Stewart EE75 Mar 31 at 16:51

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